NCN1154MUTGEVB
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5
NCN1154 − COMPONENTS SELECTION
Input Capacitor
A 0.1 mF X5R ceramic capacitor or larger must bypass Vcc input to the ground. This capacitor should be placed as close as
possible to this input.
ESD Diode
These devices have limited built−in ESD protection, an external bi−directional ESD / IEC diode is recommended on COM+
and COM− pin. The demoboard includes six additional ESD diodes for test purpose which are not required by the application.
The ESD11N is designed to protect voltage sensitive components that require ultra−low capacitance from ESD and transient
voltage events. Excellent clamping capability, low capacitance, low leakage, and fast response time, make these parts ideal for
ESD protection on designs where board space is at a premium. Because of its low capacitance, it is suited for use in high
frequency designs such as USB 2.0 high speed and antenna line applications.
NCN1154 – BILL OF MATERIAL
Designator Qty Description Value Tolerance Footprint Manufacturer
Manufacturer
Part Number
U1 1 IC, High Speed Switches NA NA UDFN−12 ON Semiconductor NCN1154
D1, D2, D4, D5, D6, D8,
D10, D12
8 ESD Diode NA NA 0.6 x 0.3 mm ON Semiconductor ESD11N5.0ST5G
C1, C3 1 Ceramic capacitor 10 nF $20% 0402 AVX Corporation 04023C103KAT2A
C2 1 Ceramic capacitor
1 mF
$20% 0603 Murata GRM188R61C105
J6 1 USB Connector Male ANG
Receptable
NA NA A Type Mill−Max 896−43−004−90−000000
J4, J5 2 USB Connector Male
VERT Receptable
NA NA B Type Molex/Waldom 67265−2001
BJ6 1 Single Banana NA NA NA Pomona Electronics 2142−6
BJ12 1 Single Banana NA NA NA Pomona Electronics 2142−9
BJ 1 Double Banana NA NA NA Pomona Electronics 2143−0
SW1, SW2 2 Switch NA NA NA ITT CANNON OS103011MS8QP1
PCB 1 5.0 x 5.0 x 0.25 mm
2 Layers
NA NA NA Any EBT1745−01 REV: A
NCN1154 − PCB LAYOUT GUIDELINES
Electrical Layout Considerations
Implementing a high speed USD device requires paying attention on USB lines and traces to preserve signal integrity. The
demonstration board serves as layout example and can support the design engineers to preserve high speed performances.
Electrical layout guidelines are:
− The bypass capacitor must be placed as close as possible to the Vcc input pin for noise immunity.
− The characteristic impedance of each High Speed USB segment must be 45 W.
− All corresponding D+ / D− line segment pairs must be the same length.
− The use of vias to route these signals should be avoided.
− The use of turns or bends to route these signal should be avoided.
− The ground plane of the PCB will be used to determine the characteristics impedance of each line.
