TS3809/3810 Series
Taiwan Semiconductor
Document Number: DS_P0000206
6 Version: E15
APPLICATION INFORMATION
Negative-Going V
CC
transients in addition to issuing a reset to the µP during power-up, power-down, and brownout
conditions, the TS3809/3810 are relatively immune to short-duration negative-going V
CC
transients (glitches).
The TS3809/3810 does not generate a reset pulse. The graph was generated using a negative going pulse applied
to V
CC
, starting 0.5V above the actual reset threshold and ending below it by the magnitude indicated (reset
comparator overdrive). The graph indicates the maximum pulse width a negative going V
CC
transient can have
without causing a reset pulse. As the magnitude of the transient increases (goes farther below the reset threshold),
the maximum allowable pulse width decreases. Typically, a V
CC
transient that goes 100mV below the reset
threshold and lasts 20µS or less will not cause a reset pulse. A 0.1µF bypass capacitor mounted as close as
possible to the V
CC
pin provides additional transient immunity.
FU
NCTION DESCRIPTION
A microprocessor’s reset input starts the µP in a known state. The TS3809/3810 assert reset to prevent code-
execution errors during power-up, power-down, or brownout conditions. They assert a reset signal whenever the
V
CC
supply voltage declines below a preset threshold, keeping it asserted for at least 140ms after V
CC
has risen
above the reset threshold. The TS3809/3810 have a push-pull output stage.
ENSURING A VALID RESET OUTPUT DOWN TO V
CC
=0
RESET is guaranteed to be a logic low for V
CC
> 1.0V. Once V
CC
exceeds the reset threshold, an internal timer
keeps RESET low for the reset timeout period; after this interval, RESET goes high. If a brownout condition occurs
(V
CC
dips below the reset threshold), RESET goes low. Any time V
CC
goes below the reset threshold, the internal
timer resets to zero, and RESET goes low. The internal timer starts after V
CC
returns above the reset threshold, and
RESET remains low for the reset timeout period. When V
CC
falls below 1V, the TS3809/3810 reset output no longer
sinks current - it becomes an open circuit. Therefore, high impedance CMOS logic input connected to reset can
drift to undetermined voltages. This present no problem in most applications since most µP and other circuitry is
inoperative with V
CC
below 1V.However, in applications where reset must be valid down to 0V, adding a pull down
re
sistor to reset causes and stray leakage currents to flow to ground, holding reset low (Figure 2.) R1’s value is not
critical; 100K is large enough not to load reset and small enough to pull RESET to ground. For the TS3809/3810 if
reset is required to remain valid for V
CC
<1V.
BENEFITS OF HIGHLY ACCURATE RESET THRESHOLD
Most µP supervisor ICs has reset threshold voltages between 5% and 10% below the value of nominal supply
voltages. This ensures a reset will not occur within 5% of the nominal supply, but will occur when the supply is 10%
below nominal. When using ICs rated at only the nominal supply ±5%, this leaves a zone of uncertainty where the
supply is between 5% and 10% low, and where the reset many or may not be asserted.
TIMMING DIAGRAM
TS3809CXA/B/C/G RFG
TS3810CXA/B/C/D/E/F/G RFG
Not Recommeded
