74ABT16646CMTDX

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74ABT16646
Skew
(SOIC Package)
Note 13: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 14: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load.
Note 15: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH to LOW (t
OSHL
), LOW to HIGH (t
OSLH
), or any combination switching LOW to HIGH and/or HIGH to
LOW (t
OST
). This specification is guaranteed but not tested.
Note 16: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all
the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Note 17: Propagation delay variation for a given set of conditions (i.e., temperature and V
CC
) from device to device. This specification is guaranteed but not
tested.
Capacitance
Note 18: C
I/O
is measured at frequency, f = 1 MHz, per MIL-STD-883, Method 3012.
Symbol Parameter
T
A
= 40°C to +85°CT
A
= 40°C to +85°C
Units
V
CC
= 4.5V5.5V V
CC
= 4.5V5.5V
C
L
= 50 pF C
L
= 250 pF
16 Outputs Switching 16 Outputs Switching
(Note 13) (Note 14)
Max Max
t
OSHL
Pin to Pin Skew
2.0 2.5 ns
(Note 15) HL Transitions
t
OSLH
Pin to Pin Skew
2.0 2.5 ns
(Note 15) LH Transitions
t
PS
Duty Cycle
2.0 2.5
(Note 16) LHHL Skew
t
OST
Pin to Pin Skew
2.8 3.0 ns
(Note 15) LH/HL Transitions
t
PV
Device to Device Skew
3.5 4.0 ns
(Note 17) LH/HL Transitions
Symbol Parameter Typ Units
Conditions
T
A
= 25°C
C
IN
Input Capacitance 5 pF V
CC
= 0V (non I/O pins)
C
I/O
(Note 18) Output Capacitance 11 pF V
CC
= 5.0V (A
n
, B
n
)
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74ABT16646
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Package Number MS56A
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74ABT16646 16-Bit Transceivers and Registers with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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74ABT16646CMTDX

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC TXRX NON-INVERT 5.5V 56TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
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