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TIME SLOT ASSIGNMENT/ORGANIZATION
On-board counters establish when PCM and ADPCM I/O occur. The counters are programmed by the
time slot registers. Time slot size (number of bits wide) is determined by the state of CP/ EX . The number
of time slots available is determined by the state of both CP/ EX and U/
A
(Figures 7 through 10). For
example, if the X channel is set to compress (CP/ EX = 1) and it is set to expect m-law data
(U/
A
= 1), then the input port (XIN) is set up for 32 8-bit time slots and the output port (XOUT) is set up
for 64 4-bit time slots. The time slot organization is not dependent on which algorithm has been selected.
Note: Time slots are counted from the frame sync signal starting at the first rising edge of either CLKX
or CLKY after the frame sync.
Figure 7. m-LAW PCM INTERFACE
Figure 8. m-LAW ADPCM INTERFACE
DS2165Q
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Figure 9. A-LAW PCM INTERFACE
Figure 10. A-LAW ADPCM INTERFACE
DS2165Q
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HARDWARE MODE
The hardware mode is intended for applications that do not have an external controller available or do not
require the extended features offered by the serial port. Connecting the SPS pin to V
SS
disables the serial
port, clears all internal register bits, and maps the IPD, U/
A
, and CP/ EX bits for both channels to external
bits (Table 3). In the hardware mode, both the input and output time slots default to time slot 0.
Table 3. HARDWARE MODE
PIN
# NAME
REGISTER LOCATION FUNCTION
6A0
CP/ EX
(Channel X)
Channel X Coding Configuration
0 = Expand
1 = Compress
7A1
AS0/AS1/AS2
(Channel X and Y)
Algorithm Select (Table 4)
8A2
U/
A
(Channel X)
Channel X Data Format
0 = A-law
1 = m-law
9A3
CP/ EX
(Channel Y)
Channel Y Coding Configuration
0 = Expand
1 = Compress
10 A4
AS0/AS1/AS2
(Channel X and Y)
Algorithm Select (Table 4)
11 A5
U/
A
(Channel Y)
Channel Y Data Format
0 = A-law
1 = m-law
22 SDI
IPD
(Channel Y)
Channel Y Idle Select
0 = Channel Active
1 = Channel Idle
23
CS
IPD
(Channel X)
Channel X Idle Select
0 = Channel Active
1 = Channel Idle
NOTES:
1) SCLK must be connected to V
SS
when the hardware mode is selected.
2) When both channels are idled, power consumption is significantly reduced.
3) The NIL powers up within 800ms after either channel is returned to active from an idle state.

DS2165Q+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Audio DSPs 16/24/32kbps ADPCM Processor
Lifecycle:
New from this manufacturer.
Delivery:
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