Table 12: DDR2 I
DD
Specifications and Conditions – 4GB (Die Revisions M) (Continued)
Values shown for MT47H256M4 DDR2 SDRAM only and are computed from values specified in the 1Gb (256 Meg x 4) com-
ponent data sheet
Parameter Symbol
-80E/
-800 -667 Units
Active power-down current: All device banks open;
t
CK =
t
CK
(I
DD
); CKE is LOW; Other control and address bus inputs are stable;
Data bus inputs are floating
Fast PDN exit
MR[12] = 0
I
DD3P
2
1008 1008 mA
Slow PDN exit
MR[12] = 1
720 720
Active standby current: All device banks open;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX
(I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Other con-
trol and address bus inputs are switching; Data bus inputs are switching
I
DD3N
2
1188 1080 mA
Operating burst write current: All device banks open; Continuous burst writes;
BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX (I
DD
),
t
RP =
t
RP (I
DD
);
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;
Data bus inputs are switching
I
DD4W
1
2430 2250 mA
Operating burst read current: All device banks open; Continuous burst read, I
OUT
= 0mA; BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX (I
DD
),
t
RP =
t
RP
(I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
switching; Data bus inputs are switching
I
DD4R
1
2340 2160 mA
Burst refresh current:
t
CK =
t
CK (I
DD
); REFRESH command at every
t
RFC (I
DD
) inter-
val; CKE is HIGH, S# is HIGH between valid commands; Other control and address
bus inputs are switching; Data bus inputs are switching
I
DD5
2
2970 2880 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus
inputs are floating; Data bus inputs are floating
I
DD6
2
252 252 mA
Operating bank interleave read current: All device banks interleaving reads,
I
OUT
= 0mA; BL = 4, CL = CL (I
DD
), AL =
t
RCD (I
DD
) - 1 ×
t
CK (I
DD
);
t
CK =
t
CK (I
DD
),
t
RC =
t
RC (I
DD
),
t
RRD =
t
RRD (I
DD
),
t
RCD =
t
RCD (I
DD
); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are stable during deselects; Data bus inputs are
switching
I
DD7
1
3960 3510 mA
Notes:
1. Value calculated as one module rank in this operating condition. All other module ranks
in I
DD2P
(CKE LOW) mode.
2. Value calculated reflects all module ranks in this operating condition.
Table 13: DDR2 I
DD
Specifications and Conditions – 8GB (Die Revision C)
Values shown for MT47H512M4 DDR2 SDRAM only and are computed from values specified in the 2Gb (512 Meg x 4) com-
ponent data sheet
Parameter Symbol
-80E/
-800 -667 Units
Operating one bank active-precharge current:
t
CK =
t
CK (I
DD
),
t
RC =
t
RC (I
DD
),
t
RAS =
t
RAS MIN (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address
bus inputs are switching; Data bus inputs are switching
I
DD0
1
1566 1476 mA
Operating one bank active-read-precharge current: I
OUT
= 0mA; BL = 4, CL =
CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RC =
t
RC (I
DD
),
t
RAS =
t
RAS MIN (I
DD
),
t
RCD =
t
RCD
(I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
switching; Data pattern is same as I
DD4W
I
DD1
1
1764 1656 mA
2Gb, 4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
I
DD
Specifications
PDF: 09005aef83d65c27
htf36c256_512_1gx72pz.pdf - Rev. E 4/14 EN
13
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