OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

70V261S35PF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
6.42
IDT70V261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Industrial and Commercial Temperature Ranges
7
Waveform of Read Cycles
(5)
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage
(5)
NOTES:
1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = V
IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for t
DH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual t
DH will always be smaller than the actual tOW.
5. 'X' in part number indicates power rating (S or L).
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.
2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB.
3. t
BDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no
relation to valid output data.
4. Start of valid data depends on which timing becomes effective last t
AOE, tACE, tAA or tBDD.
5. SEM = V
IH.
t
RC
R/W
CE
ADDR
t
AA
OE
UB, LB
3040 drw
0
(4)
t
ACE
(4)
t
AOE
(4)
t
ABE
(4)
(1)
t
LZ
t
OH
(2)
t
HZ
(3,4)
t
BDD
DATA
OUT
BUSY
OUT
VALID DATA
(4)
Symbol Parameter
70V261X25
Com'l
& Ind
70V261X35
Com'l Only
70V261X55
Com'l Only
UnitMin. Max. Min. Max. Min. Max.
WRI TE CYCLE
t
WC
Write Cycle Time 25
____
35
____
55
____
ns
t
EW
Chip Enable to End-of-Write
(3 )
20
____
30
____
45
____
ns
t
AW
Address Valid to End-of-Write 20
____
30
____
45
____
ns
t
AS
Address Set-up Time
(3 )
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 20
____
25
____
40
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
ns
t
DW
Data Valid to End -of-Write 15
____
20
____
30
____
ns
t
HZ
Output High-Z Time
(1,2)
____
15
____
20
____
25 ns
t
DH
Data Hold Time
(4 )
0
____
0
____
0
____
ns
t
WZ
Write Enabl e to Output in High-Z
(1,2)
____
15
____
20
____
25 ns
t
OW
Output Active from End-of-Write
(1 , 2,4 )
0
____
0
____
0
____
ns
t
SWRD
SEM Flag Write to Read Time
5
____
5
____
5
____
ns
t
SPS
SEM Flag Contention Window
5
____
5
____
5
____
ns
3040 tbl 12
6.42
IDT70V261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Industrial and Commercial Temperature Ranges
8
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing
(1,5,8)
NOTES:
1. R/W or CE or UB and LB must be HIGH during all address transitions.
2. A write occurs during the overlap (t
EW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. t
WR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of t
WP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the
bus for the required t
DW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
9. To access RAM, CE = V
IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing
(1,5)
R/W
t
WC
t
HZ
t
AW
t
WR
t
AS
t
WP
DATA
OUT
(2)
t
WZ
t
DW
t
DH
t
OW
OE
ADDRESS
DATA
IN
(6)
(4) (4)
(7)
CE or SEM
3040 drw 07
(9)
CE or SEM
(9)
(7)
(3)
3040 drw 08
t
WC
t
AS
t
WR
t
DW
t
DH
ADDRESS
DATA
IN
R/W
t
AW
t
EW
UB or LB
(3)
(2)
(6)
CE or SEM
(9)
(9)
6.42
IDT70V261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Industrial and Commercial Temperature Ranges
9
SEM
3040 drw 09
t
AW
t
EW
t
SOP
I/O
0
VALID ADDRESS
t
SAA
R/W
t
WR
t
OH
t
ACE
VALID ADDRESS
DATA
IN
VALID
DATA
OUT
t
DW
t
WP
t
DH
t
AS
t
SWRD
t
AOE
Read CycleWrite Cycle
A
0
-A
2
OE
VALID
(2)
Timing Waveform of Semaphore Read after Write Timing, Either Side
(1)
NOTES:
1. D
OR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH.
2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/W
"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If t
SPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
Timing Waveform of Semaphore Write Contention
(1,3,4)
NOTES:
1. CE = V
IH or UB & LB = VIH for the duration of the above timing (both write and read cycle).
2. “DATA
OUT VALID” represents all I/O's (I/O0-I/O15) equal to the semaphore value.
SEM
"A"
3040 drw 10
t
SPS
MATCH
R/W
"A"
MATCH
A
0"A"
-A
2"A"
SIDE
"A"
(2)
SEM
"B"
R/W
"B"
A
0"B"
-A
2"B"
SIDE
(2)
"B"
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

70V261S35PF

Mfr. #:
Buy 70V261S35PF
Manufacturer:
IDT
Description:
SRAM 16Kx16,3.3V DUAL- PORT RAM w/INT
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet