CS1500
2 DS849F1
Nov ?$shortyear>
CONFIDENTIAL
1. INTRODUCTION
Figure 1. CS1500 Block Diagram
The CS1500 digital power factor controller operates in variable
on-time, variable frequency, discontinuous conduction mode
(DCM). The CS1500 uses a proprietary digital algorithm to
maximize the efficiency and reduce the conductive EMI.
The analog-to-digital converter (ADC) shown in the CS1500
block diagram in Figure 9 is used to sense the PFC output
voltage ( V
link
) and the rectified AC line voltage ( V
rect
) by
measuring currents through their respective resistors. The
magnitudes of these currents are measured as a proportion of a
reference current (I
REF
) that functions as the reference for the
ADCs. The digital signal is then processed in a control algorithm
which determines the behavior of the CS1500 during start-up,
normal operation, and under fault conditions, such as
overvoltage, and over-temperature conditions.
The CS1500 PFC switching frequency varies with the V
rect
on
a cycle-by-cycle basis, and its digital algorithm calculates the
on-time accordingly for unity power factor. Unlike traditional
Critical Conduction Mode (CRM) PFC controller, CS1500
operates at its low switching frequency near the zero-crossing
point of the AC input voltage, and it operates at its high
switching frequency at the peak of its AC input voltage (this is
the opposite of the switching frequency profile for a CRM PFC
controller), thus CS1500 reduces switching losses especially
under light-load conditions, spreads conducted EMI energy
peaks over a wide frequency band and increases overall
system efficiency.
The proprietary digital control engine optimizes the feedback
error signal using an adaptive control algorithm, improves
system stability and transient response. No external feedback
error signal compensation components are required.
The CS1500s digital controller algorithm limits the ON time of
the Power MOSFET by the following equation:
Where T
on
is the max time that the power MOSFET is turned
on and V
rect
is the rectified line voltage. In the event of a
sudden line surge or sporadic, high dv/dt line voltages, this
equation may not limit the ON time appropriately. For this type
of line disturbance, additional protection mechanisms such as
fusible resistors, fast-blow fuses, or other current-limiting
devices are recommended.
Under steady-state conditions, the voltage loop keeps PFC
output voltage close to its nominal value. Under light load
startup or feedback loop open conditions, the output voltage
may pass the overvoltage protection threshold. The digital
control engine initiates a fast response loop to shut down gate
driving signal to reduce the energy delivered to the output for
PFC capacitor protection. When the link voltage drop below
V
OVP
-V
OVP(Hy)
, PFC resumes normal operation.
V
Z
POR +
-
V
th(ST)
V
th(STP)
Voltage
Regulator
7
VDD
6
GD
5
GND
IFB
ADC
IAC
ADC
V
DD
V
DD
15k
24k
3
V
DD
15k
24k
4
T
on
0.001587VμS
V
rect
-------------------------------------
≤
