Document No. 008-0284-0 Page 2 - 3 Rev. E
Model 635
7.0mm x 5.0mm Low Jitter
LVPECL or LVDS Clock
ELECTRICAL CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT
Maximum Supply Voltage
V
CC
- -0.5 - 5.0 V
Storage Temperature
T
STG
- -40 - +100 °C
Frequency Range
LVPECL 10.00 - 320
LVDS 80.00 - 320
All Inclusive, see Note 1. - - 20, 25, 50, 100
1st year aging - - 3
Operating Temperature
Commercial -20 +70
Industrial -40 +85
2.38 2.5 2.63
3.14 3.3 3.47
Supply Current
LVPECL --88
LVDS --65
Start Up Time
T
S
Application of V
CC
-25ms
Phase Jitter tjrms Bandwidth 12 kHz - 20 MHz - 0.3 0.7
Period Jitter RMS pjrms - - 2.6 -
Period Jitter Pk-Pk - - 25 -
Enable Function Standby
Enable Input Voltage
V
IH
Pin 1 or 2 Logic '1', Output Enabled
0.7*V
CC
--
Disable Input Voltage
V
IL
Pin 1 or 2 Logic '0', Output Disabled - -
0.3*V
CC
Disable Time
T
PLZ
Pin 1 or 2 Logic '0' , Output Disabled - - 200 ns
Enable Time
T
PLZ
Pin 1 or 2 Logic '1', Output Enabled - - 2 ms
LVPECL WAVEFORM
Output Load
R
L
Terminated to V
CC
- 2.0V
-50-Ohms
Output Duty Cycle SYM
@ V
CC
- 1.3V
45 - 55 %
Output Voltage Levels
Logic '1' Level
V
OH
PECL Load, -20°C to +70°C
V
CC
- 1.025
-
V
CC
- 0.880
Logic '0' Level
V
OL
PECL Load, -20°C to +70°C
V
CC
- 1.810
-
V
CC
- 1.620
Logic '1' Level
V
OH
PECL Load, -40°C to +85°C
V
CC
- 1.085
-
V
CC
- 0.880
Logic '0' Level
V
OL
PECL Load, -40°C to +85°C
V
CC
- 1.830
-
V
CC
- 1.555
Rise and Fall Time
T
R
, T
F
@ 20% - 80% Levels - 0.3 0.7 ns
LVDS WAVEFORM
Output Load
R
L
Between Outputs - 100 - Ohms
Output Duty Cycle SYM @ 1.25V 45 - 55 %
Differential Output Voltage
V
OD
R
L
= 100 Ohms
247 350 454 mV
Offset Voltage
V
OS
LVDS Load 1.125 1.25 1.375 V
Output Voltage Levels
Logic '1' Level
V
OH
LVDS Load - 1.43 1.60
Logic '0' Level
V
OL
LVDS Load 0.90 1.10 -
Rise and Fall Time
T
R
, T
F
@ 20% - 80% Levels - 0.4 0.7 ns
Notes:
1. Inclusive of initial tolerance at time of shipment, changes in supply voltage, load, temperature and 1st year aging.
ps
V
V
V
V
V
I
CC
Maximum Load mA
25
Supply Voltage
V
CC
± 5 %
ELECTRICAL PARAMETERS
f
O
- MHz
Frequency Stability
Δf/f
O
± ppm
T
A
- °C
LVPECL/LVDS OUTPUT WAVEFORM
ENABLE TRUTH TABLE
PIN 1 or Pin 2 PIN 4 & 5
Logic ‘1’ Output
Open Output
Logic ‘0’ High Z