56 Copyright 2010 Cirrus Logic (All Rights Reserved) DS515F2
EP9312
Universal Platform SOC Processor
Pin List
The following Plastic Ball Grid Array (PBGA) ball assignment table is sorted in order of ball.
Ball Signal Ball Signal Ball Signal Ball Signal
A1 CSN[7] E9 RVDD L3 DA[16] T13 CVDD
A2 DA[28]
E10 GND L4 DA[15] T14 GND
A3 AD[18]
E11 GND L5 GND T15 INT[0]
A4 DD[8]
E12 RVDD L8 GND T16 USBM[1]
A5 DD[4]
E13 CVDD L9 GND T17 RXD[0]
A6 AD[17]
E14 CVDD L10 GND T18 TXD[2]
A7 RDN
E15 GND L11 GND T19 ROW[2]
A8 RXCLK
E16 ASDI L12 GND T20 ROW[4]
A9 MIIRXD[0]
E17 DIOWN L13 GND U1 AD[0]
A10 RXDVAL
E18 EGPIO[0] L16 CVDD U2 P[15]
A11 MIITXD[2]
E19 EGPIO[3] L17 COL[5] U3 P[10]
A12 TXERR
E20 EGPIO[5] L18 COL[7] U4 P[7]
A13 CLD
F1 SDCSN[3] L19 RSTON U5 P[6]
A14 NC
F2 DA[22] L20 PRSTN U6 P[4]
A15 NC
F3 DA[24] M1 AD[7] U7 P[0]
A16 NC
F4 AD[25] M2 DA[14] U8 AD[13]
A17 EGPIO[12]
F5 RVDD M3 AD[6] U9 DA[3]
A18 EGPIO[15]
F6 GND M4 AD[5] U10 DA[0]
A19 NC
F7 CVDD M5 CVDD U11 DSRN
A20 NC
F14 CVDD M8 GND U12 BOOT[1]
B1 CSN[2]
F15 GND M9 GND U13 NC
B2 DA[31]
F16 GND M10 GND U14 SSPRX1
B3 DA[30]
F17 EGPIO[2] M11 GND U15 INT[1]
B4 DA[27]
F18 EGPIO[4] M12 GND U16 PWMOUT
B5 DD[7]
F19 EGPIO[6] M13 GND U17 USBM[0]
B6 DD[3]
F20 EGPIO[8] M16 GND U18 RXD[1]
B7 WRN
G1 SDCSN[0] M17 COL[4] U19 TXD[1]
B8 MDIO
G2 SDCSN[1] M18 COL[3] U20 ROW[1]
B9 MIIRXD[1]
G3 SDWEN M19 COL[6] V1 P[16]
B10 RXERR
G4 SDCLK M20 CSN[0] V2 P[11]
B11 MIITXD[1]
G5 RVDD N1 DA[13] V3 P[8]
B12 CRS
G6 RVDD N2 DA[12] V4 DD[15]
B13 NC
G15 RVDD N3 DA[11] V5 DD[13]
B14 NC
G16 RVDD N4 AD[3] V6 P[1]
B15 NC
G17 EGPIO[7] N5 CVDD V7 AD[14]
B16 NC
G18 EGPIO[9] N6 CVDD V8 AD[12]
B17 EGPIO[13]
G19 EGPIO[10] N8 GND V9 DA[2]
B18 NC
G20 EGPIO[11] N9 GND V10 IDECS0N
B19 WAITN
H1 DQMN[3] N10 GND V11 IDEDA[2]
B20 TRSTN
H2 CASN N11 GND V12 TDI
C1 CSN[1]
H3 RASN N12 GND V13 GND
C2 CSN[3]
H4 SDCSN[2] N13 GND V14 ASYNC