DS515F2 Copyright 2010 Cirrus Logic (All Rights Reserved) 55
EP9312
Universal Platform SOC
Figure 40. 352 PIN BGA PINOUT
1 23 4 5678910111213141516171819 20
Y HSYNC DD[1] DD[12] P[2] AD[15] DA[6] DA[4]
AD[10
]
DA[1] AD[8]
IDEDA[
0]
DTRN TDO BOOT[0] EEDAT ASDO SFRM1 RDLED USBP[1] ABITCLK Y
W P[12] P[9] DD[0] P[5] P[3] DA[7] DA[5]
AD[11
]
AD[9]
IDECS1
N
IDEDA[
1]
TCK TMS EECLK SCLK1 GRLED INT[3] SLA[1] SLA[0] RXD[2] W
V P[16] P[11] P[8] DD[15] DD[13] P[1]
AD[1
4]
AD[12
]
DA[2]
IDECS0
N
IDEDA[
2]
TDI GND ASYNC SSPTX1 INT[2] RTSN USBP[0] CTSN TXD[0] V
U AD[0] P[15] P[10] P[7] P[6] P[4] P[0]
AD[13
]
DA[3] DA[0] DSRN BOOT[1] NC SSPRX1 INT[1]
PWMO
UT
USBM[0] RXD[1] TXD[1] ROW[1] U
T DA[8] BLANK P[13] SPCLK
V_CSY
NC
DD[1
4]
GND
CVD
D
RVDD GND GND RVDD CVDD GND INT[0]
USBM[1
]
RXD[0] TXD[2] ROW[2] ROW[4] T
R AD[2] AD[1] P[17] P[14] RVDD
RVD
D
GND
CVD
D
CVDD GND RVDD RVDD ROW[0] ROW[3]
PLL_GN
D
ROW[5] R
P AD[4] DA[10] DA[9] BRIGHT RVDD
RVD
D
RVDD RVDD XTALI
PLL_VD
D
ROW[6] ROW[7] P
N DA[13] DA[12] DA[11] AD[3] CVDD
CVD
D
GND GND GND GND GND GND GND GND XTALO COL[0] COL[1] COL[2] N
M AD[7] DA[14] AD[6] AD[5] CVDD GND GND GND GND GND GND GND COL[4] COL[3] COL[6] CSN[0] M
L DA[18] DA[17] DA[16] DA[15] GND GND GND GND GND GND GND CVDD COL[5] COL[7] RSTON PRSTN L
K AD[22] DA[20] AD[21] DA[19] RVDD GND GND GND GND GND GND CVDD SYM SYP SXM SXP K
J DA[21]
DQMN[
0]
DQMN[
1]
DQMN[2
]
GND GND GND GND GND GND GND CVDD
RTCXTA
LI
XM YP YM J
H
DQMN[
3]
CASN RASN
SDCSN[
2]
CVDD GND GND GND GND GND GND RVDD
RTCXTA
LO
ADC_V
DD
ADC_G
ND
XP H
G
SDCSN[
0]
SDCSN[
1]
SDWE
N
SDCLK RVDD
RVD
D
RVDD RVDD EGPIO[7]
EGPIO[
9]
EGPIO[1
0]
EGPIO[11
]
G
F
SDCSN[
3]
DA[22] DA[24] AD[25] RVDD GND
CVD
D
CVDD GND GND EGPIO[2]
EGPIO[
4]
EGPIO[6
]
EGPIO[8] F
E AD[23] DA[23] DA[26] CSN[6] GND GND
CVD
D
CVD
D
RVDD GND GND RVDD CVDD CVDD GND ASDI DIOWN
EGPIO[
0]
EGPIO[3
]
EGPIO[5] E
D AD[24] DA[25] DD[11]
SDCLK
EN
AD[19] DD[9] DD[5]
AD[16
]
MIIRXD[
2]
MIITXD[
3]
TXEN NC NC NC
EGPIO[
14]
NC USBM[2] ARSTN DIORN EGPIO[1] D
C CSN[1] CSN[3] AD[20] DA[29] DD[10] DD[6] DD[2] MDC
MIIRXD[
3]
TXCLK
MIITXD[
0]
NC NC NC NC NC NC USBP[2] IORDY DMACKN C
B CSN[2] DA[31] DA[30] DA[27] DD[7] DD[3] WRN MDIO
MIIRXD[
1]
RXERR
MIITXD[
1]
CRS NC NC NC NC
EGPIO[1
3]
NC WAITN TRSTN B
A CSN[7] DA[28] AD[18] DD[8] DD[4]
AD[1
7]
RDN
RXCL
K
MIIRXD[
0]
RXDVA
L
MIITXD[
2]
TXERR CLD NC NC NC
EGPIO[1
2]
EGPIO[
15]
NC NC A
1 23 4 5678910111213141516171819 20
56 Copyright 2010 Cirrus Logic (All Rights Reserved) DS515F2
EP9312
Universal Platform SOC Processor
Pin List
The following Plastic Ball Grid Array (PBGA) ball assignment table is sorted in order of ball.
Ball Signal Ball Signal Ball Signal Ball Signal
A1 CSN[7] E9 RVDD L3 DA[16] T13 CVDD
A2 DA[28]
E10 GND L4 DA[15] T14 GND
A3 AD[18]
E11 GND L5 GND T15 INT[0]
A4 DD[8]
E12 RVDD L8 GND T16 USBM[1]
A5 DD[4]
E13 CVDD L9 GND T17 RXD[0]
A6 AD[17]
E14 CVDD L10 GND T18 TXD[2]
A7 RDN
E15 GND L11 GND T19 ROW[2]
A8 RXCLK
E16 ASDI L12 GND T20 ROW[4]
A9 MIIRXD[0]
E17 DIOWN L13 GND U1 AD[0]
A10 RXDVAL
E18 EGPIO[0] L16 CVDD U2 P[15]
A11 MIITXD[2]
E19 EGPIO[3] L17 COL[5] U3 P[10]
A12 TXERR
E20 EGPIO[5] L18 COL[7] U4 P[7]
A13 CLD
F1 SDCSN[3] L19 RSTON U5 P[6]
A14 NC
F2 DA[22] L20 PRSTN U6 P[4]
A15 NC
F3 DA[24] M1 AD[7] U7 P[0]
A16 NC
F4 AD[25] M2 DA[14] U8 AD[13]
A17 EGPIO[12]
F5 RVDD M3 AD[6] U9 DA[3]
A18 EGPIO[15]
F6 GND M4 AD[5] U10 DA[0]
A19 NC
F7 CVDD M5 CVDD U11 DSRN
A20 NC
F14 CVDD M8 GND U12 BOOT[1]
B1 CSN[2]
F15 GND M9 GND U13 NC
B2 DA[31]
F16 GND M10 GND U14 SSPRX1
B3 DA[30]
F17 EGPIO[2] M11 GND U15 INT[1]
B4 DA[27]
F18 EGPIO[4] M12 GND U16 PWMOUT
B5 DD[7]
F19 EGPIO[6] M13 GND U17 USBM[0]
B6 DD[3]
F20 EGPIO[8] M16 GND U18 RXD[1]
B7 WRN
G1 SDCSN[0] M17 COL[4] U19 TXD[1]
B8 MDIO
G2 SDCSN[1] M18 COL[3] U20 ROW[1]
B9 MIIRXD[1]
G3 SDWEN M19 COL[6] V1 P[16]
B10 RXERR
G4 SDCLK M20 CSN[0] V2 P[11]
B11 MIITXD[1]
G5 RVDD N1 DA[13] V3 P[8]
B12 CRS
G6 RVDD N2 DA[12] V4 DD[15]
B13 NC
G15 RVDD N3 DA[11] V5 DD[13]
B14 NC
G16 RVDD N4 AD[3] V6 P[1]
B15 NC
G17 EGPIO[7] N5 CVDD V7 AD[14]
B16 NC
G18 EGPIO[9] N6 CVDD V8 AD[12]
B17 EGPIO[13]
G19 EGPIO[10] N8 GND V9 DA[2]
B18 NC
G20 EGPIO[11] N9 GND V10 IDECS0N
B19 WAITN
H1 DQMN[3] N10 GND V11 IDEDA[2]
B20 TRSTN
H2 CASN N11 GND V12 TDI
C1 CSN[1]
H3 RASN N12 GND V13 GND
C2 CSN[3]
H4 SDCSN[2] N13 GND V14 ASYNC
DS515F2 Copyright 2010 Cirrus Logic (All Rights Reserved) 57
EP9312
Universal Platform SOC Processor
C3 AD[20] H5 CVDD N15 GND V15 SSPTX1
C4 DA[29]
H8 GND N16 GND V16 INT[2]
C5 DD[10]
H9 GND N17 XTALO V17 RTSN
C6 DD[6]
H10 GND N18 COL[0] V18 USBP[0]
C7 DD[2]
H11 GND N19 COL[1] V19 CTSN
C8 MDC
H12 GND N20 COL[2] V20 TXD[0]
C9 MIIRXD[3]
H13 GND P1 AD[4] W1 P[12]
C10 TXCLK
H16 RVDD P2 DA[10] W2 P[9]
C11 MIITXD[0]
H17 RTCXTALO P3 DA[9] W3 DD[0]
C12 NC
H18 ADC_VDD P4 BRIGHT W4 P[5]
C13 NC
H19 ADC_GND P5 RVDD W5 P[3]
C14 NC
H20 XP P6 RVDD W6 DA[7]
C15 NC
J1 DA[21] P15 RVDD W7 DA[5]
C16 NC
J2 DQMN[0] P16 RVDD W8 AD[11]
C17 NC
J3 DQMN[1] P17 XTALI W9 AD[9]
C18 USBP[2]
J4 DQMN[2] P18 PLL_VDD W10 IDECS1N
C19 IORDY
J5 GND P19 ROW[6] W11 IDEDA[1]
C20 DMACKN
J8 GND P20 ROW[7] W12 TCK
D1 AD[24]
J9 GND R1 AD[2] W13 TMS
D2 DA[25]
J10 GND R2 AD[1] W14 EECLK
D3 DD[11]
J11 GND R3 P[17] W15 SCLK1
D4 SDCLKEN
J12 GND R4 P[14] W16 GRLED
D5 AD[19]
J13 GND R5 RVDD W17 INT[3]
D6 DD[9]
J16 CVDD R6 RVDD W18 SLA[1]
D7 DD[5]
J17 RTCXTALI R7 GND W19 SLA[0]
D8 AD[16]
J18 XM R8 CVDD W20 RXD[2]
D9 MIIRXD[2]
J19 YP R13 CVDD Y1 HSYNC
D10 MIITXD[3]
J20 YM R14 GND Y2 DD[1]
D11 TXEN
K1 AD[22] R15 RVDD Y3 DD[12]
D12 NC
K2 DA[20] R16 RVDD Y4 P[2]
D13 NC
K3 AD[21] R17 ROW[0] Y5 AD[15]
D14 NC
K4 DA[19] R18 ROW[3] Y6 DA[6]
D15 EGPIO[14]
K5 RVDD R19 PLL_GND Y7 DA[4]
D16 NC
K8 GND R20 ROW[5] Y8 AD[10]
D17 USBM[2]
K9 GND T1 DA[8] Y9 DA[1]
D18 ARSTN
K10 GND T2 BLANK Y10 AD[8]
D19 DIORN
K11 GND T3 P[13] Y11 IDEDA[0]
D20 EGPIO[1]
K12 GND T4 SPCLK Y12 DTRN
E1 AD[23]
K13 GND T5 V_CSYNC Y13 TDO
E2 DA[23]
K16 CVDD T6 DD[14] Y14 BOOT[0]
E3 DA[26]
K17 SYM T7 GND Y15 EEDAT
E4 CSN[6]
K18 SYP T8 CVDD Y16 ASDO
E5 GND
K19 SXM T9 RVDD Y17 SFRM1
E6 GND
K20 SXP T10 GND Y18 RDLED
E7 CVDD
L1 DA[18] T11 GND Y19 USBP[1]
E8 CVDD
L2 DA[17] T12 RVDD Y20 ABITCLK
Ball Signal Ball Signal Ball Signal Ball Signal

EP9312-IBZ

Mfr. #:
Manufacturer:
Cirrus Logic
Description:
Microprocessors - MPU IC Universal Platfrm ARM9 SOC Prcessor
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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