ISL6605CRZA

4
FN9091.7
May 9, 2006
Absolute Maximum Ratings Recommended Operating Conditions
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
Input Voltage (V
EN
, V
PWM
) . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V
BOOT Voltage (V
BOOT
). . . . . . . -0.3V to 22V (DC) or 33V (<200ns)
BOOT To PHASE Voltage (V
BOOT-PHASE
) . . . . . . . . . . -0.3V to 7V
PHASE Voltage . . . . . . . . . . . . . . GND - 0.3V (DC) to 28V (<200ns)
. . . . . . . . . . GND - 5V (<100ns Pulse Width, 10μJ) to 28V (<200ns)
UGATE Voltage . . . . . . . . . . . V
PHASE
- 0.3V (DC) to V
BOOT
+0.3V
. . . . . . . V
PHASE
- 4V (<200ns Pulse Width, 20μJ) to V
BOOT
+0.3V
LGATE Voltage . . . . . . . . . . . . . . GND - 0.3V (DC) to V
VCC
+ 0.3V
. . . . . . . . . . . GND - 2V (<100ns Pulse Width, 4μJ) to V
VCC
+ 0.3V
Ambient Temperature Range. . . . . . . . . . . . . . . . . . .-40°C to 125°C
ESD Rating
HBM Class 1 JEDEC STD
Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-40°C to 85°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . 125°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%
Thermal Information
Thermal Resistance (Notes 1, 2, & 3) θ
JA
(°C/W) θ
JC
(°C/W)
SOIC Package (Note 1) . . . . . . . . . . . . 110 N/A
QFN Package (Notes 2, 3). . . . . . . . . . 95 36
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.
3. θ
JC
, "case temperature" location is at the center of the package underside exposed pad. See Tech Brief TB379 for details.
Electrical Specifications These specifications apply for T
A
= -40°C to 85°C, unless otherwise noted
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
VCC SUPPLY CURRENT
Bias Supply Current I
VCC
EN = LOW, T
A
= 0°C to 70°C - - 1.5 μA
EN = LOW, T
A
= -40°C to 85°C - - 2 μA
Bias Supply Current I
VCC
PWM pin floating, V
VCC
= 5V - 30 - μA
PWM INPUT
Input Current I
PWM
V
PWM
= 5V - 250 - μA
V
PWM
= 0V - -250 - μA
PWM Three-State Rising Threshold V
VCC
= 5V, T
A
= 0°C to 70°C - - 1.70 V
V
VCC
= 5V, T
A
= -40°C to 85°C - - 1.75 V
PWM Three-State Falling Threshold V
VCC
= 5V 3.3 - - V
Three-State Shutdown Holdoff Time V
VCC
= 5V, temperature = 25°C - 420 - ns
EN INPUT
EN LOW Threshold 1.0 - - V
EN HIGH Threshold --2.0V
SWITCHING TIME
UGATE Rise Time t
RUGATE
V
VCC
= 5V, 3nF Load - 8 - ns
LGATE Rise Time t
RLGATE
V
VCC
= 5V, 3nF Load - 8 - ns
UGATE Fall Time t
FUGATE
V
VCC
= 5V, 3nF Load - 8 - ns
LGATE Fall Time t
FLGATE
V
VCC
= 5V, 3nF Load - 4 - ns
UGATE Turn-Off Propagation Delay t
PDLUGATE
V
VCC
= 5V, 3nF Load - 8 - ns
LGATE Turn-Off Propagation Delay t
PDLLGATE
V
VCC
= 5V, 3nF Load - 8 - ns
OUTPUT
Upper Drive Source Resistance R
UGATE
500mA Source Current - 1.0 2.5 Ω
Upper Driver Source Current (Note 4) I
UGATE
V
UGATE-PHASE
= 2.5V - 2.0 - A
Upper Drive Sink Resistance R
UGATE
500mA Sink Current - 1.0 2.5 Ω
Upper Driver Sink Current (Note 4) I
UGATE
V
UGATE-PHASE
= 2.5V - 2.0 - A
Lower Drive Source Resistance R
LGATE
500mA Source Current - 1.0 2.5 Ω
Lower Driver Source Current (Note 4) I
LGATE
V
LGATE
= 2.5V - 2.0 - A
Lower Drive Sink Resistance R
LGATE
500mA Sink Current - 0.4 1.0 Ω
Lower Driver Sink Current (Note 4) I
LGATE
V
LGATE
= 2.5V - 4.0 - A
NOTE:
4. Guaranteed by design. Not 100% tested in production.
ISL6605
5
FN9091.7
May 9, 2006
Functional Pin Description
Note: Pin numbers refer to the SOIC package. Check
PINOUT diagrams for QFN pin numbers.
UGATE (Pin 1)
Upper gate drive output. Connect to gate of high-side power
N-Channel MOSFET.
BOOT (Pin 2)
Floating bootstrap supply pin for the upper gate drive.
Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to
turn on the upper MOSFET. See the Bootstrap Diode and
Capacitor section under DESCRIPTION for guidance in
choosing the appropriate capacitor value.
PWM (Pin 3)
The PWM signal is the control input for the driver. The PWM
signal can enter three distinct states during operation (see the
three-state PWM Input section under DESCRIPTION for further
details). Connect this pin to the PWM output of the controller.
GND (Pin 4)
Ground pin. All signals are referenced to this node.
LGATE (Pin 5)
Lower gate drive output. Connect to gate of the low-side
power N-Channel MOSFET.
VCC (Pin 6)
Connect this pin to a +5V bias supply. Place a high quality
bypass capacitor from this pin to GND.
EN (Pin 7)
Enable input pin. Connect this pin to HIGH to enable and
LOW to disable the IC. When disabled, the IC draws less
than 1μA bias current.
PHASE (Pin 8)
Connect this pin to the source of the upper MOSFET and the
drain of the lower MOSFET. This pin provides a return path
for the upper gate driver.
Thermal Pad (in QFN only)
In the QFN package, the pad underneath the center of the
IC is a thermal substrate. The PCB “thermal land” design
for this exposed die pad should include thermal vias that
drop down and connect to one or more buried copper
plane(s). This combination of vias for vertical heat escape
and buried planes for heat spreading allows the QFN to
achieve its full thermal potential. This pad should be either
grounded or floating, and it should not be connected to
other nodes. Refer to TB389 for design guidelines.
Description
Operation
Designed for speed, the ISL6605 MOSFET driver controls both
high-side and low-side N-Channel FETs from one externally
provided PWM signal.
A rising edge on PWM initiates the turn-off of the lower
MOSFET (see Timing Diagram). After a short propagation
delay [t
PDLLGATE
], the lower gate begins to fall. Typical fall
times [t
FLGATE
] are provided in the Electrical Specifications
section. Adaptive shoot-through circuitry monitors the
LGATE voltage and determines the upper gate delay time
[t
PDHUGATE
] based on how quickly the LGATE voltage
drops below 1V. This prevents both the lower and upper
MOSFETs from conducting simultaneously or shoot-
through. Once this delay period is completed the upper gate
drive begins to rise [t
RUGATE
] and the upper MOSFET turns
on.
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [t
PDLUGATE
] is encountered before the
upper gate begins to fall [t
FUGATE
]. Again, the adaptive
shoot-through circuitry determines the lower gate delay time,
t
PDHLGATE
. The upper MOSFET gate voltage is monitored
and the lower gate is allowed to rise after the upper MOSFET
gate-to-source voltage drops below 1V. The lower gate then
rises [t
RLGATE
], turning on the lower MOSFET.
Timing Diagram
PWM
UGATE
LGATE
t
PDLLGATE
t
FLGATE
t
PDHUGATE
t
RUGATE
t
PDLUGATE
t
FUGATE
t
PDHLGATE
t
RLGATE
ISL6605
6
FN9091.7
May 9, 2006
This driver is optimized for voltage regulators with large step
down ratio. The lower MOSFET is usually sized much larger
compared to the upper MOSFET because the lower
MOSFET conducts for a much longer time in a switching
period. The lower gate driver is therefore sized much larger
to meet this application requirement. The 0.4Ω on-resistance
and 4A sink current capability enable the lower gate driver to
absorb the current injected to the lower gate through the
drain-to-gate capacitor of the lower MOSFET and prevent a
shoot through caused by the high dv/dt of the phase node.
Three-State PWM Input
A unique feature of the ISL6605 and other Intersil drivers is
the addition of a shutdown window to the PWM input. If the
PWM signal enters and remains within the shutdown window
for a set holdoff time, the output drivers are disabled and
both MOSFET gates are pulled and held low. The shutdown
state is removed when the PWM signal moves outside the
shutdown window. Otherwise, the PWM rising and falling
thresholds outlined in the ELECTRICAL SPECIFICATIONS
determine when the lower and upper gates are enabled.
Adaptive Shoot-Through Protection
Both drivers incorporate adaptive shoot-through protection
to prevent upper and lower MOSFETs from conducting
simultaneously and shorting the input supply. This is
accomplished by ensuring the falling gate has turned off one
MOSFET before the other is allowed to rise.
During turn-off of the lower MOSFET, the LGATE voltage is
monitored until it reaches a 1V threshold, at which time the
UGATE is released to rise. Adaptive shoot-through circuitry
monitors the upper MOSFET gate voltage during UGATE
turn-off. Once the upper MOSFET gate-to-source voltage
has dropped below a threshold of 1V, the LGATE is allowed
to rise.
Internal Bootstrap Diode
This driver features an internal bootstrap Schottky diode.
Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit.The bootstrap
capacitor can be chosen from the following equation:
where Q
GATE
is the amount of gate charge required to fully
charge the gate of the upper MOSFET. The ΔV
BOOT
term is
defined as the allowable droop in the rail of the upper drive.
The above relationship is illustrated in Figure 1.
As an example, suppose an upper MOSFET has a gate
charge, Q
GATE
, of 65nC at 5V and also assume the droop in
the drive voltage over a PWM cycle is 200mV. One will find
that a bootstrap capacitance of at least 0.125μF is required.
The next larger standard value capacitance is 0.15μF. A
good quality ceramic capacitor is recommended.
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency and total gate charge of the selected
MOSFETs. Calculating the power dissipation in the driver for
a desired application is critical to ensuring safe operation.
Exceeding the maximum allowable power dissipation level
will push the IC beyond the maximum recommended
operating junction temperature of 125°C. The maximum
allowable IC power dissipation for the SO-8 package is
approximately 800mW. When designing the driver into an
application, it is recommended that the following calculation
be performed to ensure safe operation at the desired
frequency for the selected MOSFETs. The power dissipated
by the driver is approximated as below and plotted as in
Figure 2.
where f
sw
is the switching frequency of the PWM signal. V
U
and V
L
represent the upper and lower gate rail voltage. Q
U
and Q
L
are the upper and lower gate charge determined by
MOSFET selection and any external capacitance added to
the gate pins. The I
DDQ
V
CC
product is the quiescent power
of the driver and is typically negligible.
C
BOOT
Q
GATE
ΔV
BOOT
------------------------
ΔV
BOOT
(V)
C
BOOT
(uF)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.
0
Q
GATE
= 100 nC
50nC
20nC
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
50nC
20nC
Q
GATE
=100nC
FIGURE 1. BOOTSTRAP CAPACITANCE vs. BOOT RIPPLE
VOLTAGE
Pf
sw
1.5V
U
Q
U
V
L
Q
L
+()I
DDQ
V
CC
+=
ISL6605

ISL6605CRZA

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Gate Drivers W/ANNEAL VER OF ISL6605CR
Lifecycle:
New from this manufacturer.
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