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844801AGI-24LF

P1-P3P4-P6P7-P9P10-P12P13-P13
IDT
™
/ ICS
™
LVDS 400MHZ FREQUENCY SYNTHESIZER 7 ICS844801AGI-24 REV A JANUARY 16, 2008
ICS844801I-24
FEMTOCLOCKS™ CRYSTAL-TO-LVDS 400MHZ FREQUENCY SYNTHESIZER PRELIMINARY
Figure 2. CRYSTAL INPUt INTERFACE
CRYSTAL INPUT INTERFACE
The ICS844801I-24 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2
below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error. The
optimum C1 and C2 values can be slightly adjusted for different
board layouts.
ICS84332
XTAL_IN
XTAL_OUT
X1
18pF Parallel Crystal
C2
22p
C1
22p
APPLICATION INFORMATION
POWER SUPPLY FILTERING T ECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS844801I-24
provides separate power supplies to isolate any high switch-
ing noise from the outputs to the internal PLL. V
DD
and V
DDA
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance, power
supply isolation is required.
Figure 1
illustrates how a 10Ω
resistor along with a 10µF and a .01µF bypass capacitor
should be connected to each V
DDA
pin. The 10Ω resistor can
also be replaced by a ferrite bead.
FIGURE 1. POWER SUPPLY FILTERING
10Ω
V
DDA
10µF
.01µF
3.3V or 2.5V
.01µF
V
DD
IDT
™
/ ICS
™
LVDS 400MHZ FREQUENCY SYNTHESIZER 8 ICS844801AGI-24 REV A JANUARY 16, 2008
ICS844801I-24
FEMTOCLOCKS™ CRYSTAL-TO-LVDS 400MHZ FREQUENCY SYNTHESIZER PRELIMINARY
3.3V, 2.5V LVDS DRIVER TERMINATION
A general LVDS interface is shown in
Figure 4.
In a 100Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100Ω across near
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
the receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate the
unused outputs.
R1
100
3.3V or 2.5V
100
Ω
Differential Transmission
VDD
+
-
LVDS
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in
Figure 3.
The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise. This configuration requires that the output
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by removing
R1 and making R2 50Ω.
R2
Zo = 50
VDD
Ro
Zo = Ro + Rs
R1
VDD
XTAL_I N
XTAL_OU T
.1uf
Rs
IDT
™
/ ICS
™
LVDS 400MHZ FREQUENCY SYNTHESIZER 9 ICS844801AGI-24 REV A JANUARY 16, 2008
ICS844801I-24
FEMTOCLOCKS™ CRYSTAL-TO-LVDS 400MHZ FREQUENCY SYNTHESIZER PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS844801I-24.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS844801I-24 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
· Power_
MAX
= V
DD_MAX
* I
DD_MAX
= 3.465V * 80mA = 277.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125°C.
The equation for Tj is as follows: Tj = θ
JA
* Pd_total + T
A
Tj = Junction Temperature
θ
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
JA
must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.277W * 90.5°C/W = 110.1°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and
the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE
θθ
θθ
θ
JA
FOR 8 LEAD TSSOP, FORCED CONVECTION
θθ
θθ
θ
JA
by Velocity (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W
P1-P3P4-P6P7-P9P10-P12P13-P13

844801AGI-24LF

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Description:
Clock Synthesizer / Jitter Cleaner 1 LVDS OUT SYNTHESIZER
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