TDA8920C_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 11 June 2009 4 of 39
NXP Semiconductors
TDA8920C
2 × 110 W class-D power amplifier
7. Pinning information
7.1 Pinning
Fig 2. Pin configuration TDA8920CTH Fig 3. Pin configuration TDA8920CJ
TDA8920CTH
VSSD VSSA
VDDP2 SGND
BOOT2 VDDA
OUT2 IN2M
VSSP2 IN2P
n.c. MODE
STABI OSC
VSSP1 IN1P
OUT1 IN1M
BOOT1 n.c.
VDDP1 n.c.
PROT n.c.
001aai853
24
23
22
21
20
19
18
17
16
15
14
13
11
12
9
10
7
8
5
6
3
4
1
2
TDA8920CJ
OSC
IN1P
IN1M
n.c.
n.c.
n.c.
PROT
VDDP1
BOOT1
OUT1
VSSP1
STABI
VSSP2
OUT2
BOOT2
VDDP2
VSSD
VSSA
SGND
VDDA
IN2M
IN2P
MODE
001aai854
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
TDA8920C_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 11 June 2009 5 of 39
NXP Semiconductors
TDA8920C
2 × 110 W class-D power amplifier
7.2 Pin description
8. Functional description
8.1 General
The TDA8920C is a two-channel audio power amplifier that uses class-D technology.
For each channel, the audio input signal is converted into a digital PWM signal using an
analog input stage and a PWM modulator; see Figure 1. To drive the output power
transistors, the digital PWM signal is fed to a control and handshake block and to high-
and low-side driver circuits. This level-shifts the low-power digital PWM signal from a logic
level to a high-power PWM signal switching between the main supply lines.
A 2nd-order low-pass filter converts the PWM signal to an analog audio signal that can be
used to drive a loudspeaker.
Table 3. Pin description
Symbol Pin Description
TDA8920CTH TDA8920CJ
VSSA 1 18 negative analog supply voltage
SGND 2 19 signal ground
VDDA 3 20 positive analog supply voltage
IN2M 4 21 channel 2 negative audio input
IN2P 5 22 channel 2 positive audio input
MODE 6 23 mode selection input: Standby, Mute or Operating
mode
OSC 7 1 oscillator frequency adjustment or tracking input
IN1P 8 2 channel 1 positive audio input
IN1M 9 3 channel 1 negative audio input
n.c. 10 4 not connected
n.c. 11 5 not connected
n.c. 12 6 not connected
PROT 13 7 decoupling capacitor for protection (OCP)
VDDP1 14 8 channel 1 positive power supply voltage
BOOT1 15 9 channel 1 bootstrap capacitor
OUT1 16 10 channel 1 PWM output
VSSP1 17 11 channel 1 negative power supply voltage
STABI 18 12 decoupling of internal stabilizer for logic supply
n.c. 19 - not connected
VSSP2 20 13 channel 2 negative power supply voltage
OUT2 21 14 channel 2 PWM output
BOOT2 22 15 channel 2 bootstrap capacitor
VDDP2 23 16 channel 2 positive power supply voltage
VSSD 24 17 negative digital supply voltage
TDA8920C_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 11 June 2009 6 of 39
NXP Semiconductors
TDA8920C
2 × 110 W class-D power amplifier
The TDA8920C single-chip class-D amplifier contains high-power switches, drivers, timing
and handshaking between the power switches, along with some control logic. To ensure
maximum system robustness, an advanced protection strategy has been implemented to
provide overvoltage, overtemperature and overcurrent protection.
Each of the two audio channels contains a PWM modulator, an analog feedback loop and
a differential input stage. The TDA8920C also contains circuits common to both channels
such as the oscillator, all reference sources, the mode interface and a digital timing
manager.
The two independent amplifier channels feature high output power, high efficiency, low
distortion and low quiescent currents, and can be connected in the following
configurations:
Stereo Single-Ended (SE)
Mono Bridge-Tied Load (BTL)
The amplifier system can be switched to one of three operating modes using pin MODE:
Standby mode: featuring very low quiescent current
Mute mode: the amplifier is operational but the audio signal at the output is
suppressed by disabling the voltage-to-current (VI) converter input stages
Operating mode: the amplifier is fully operational, de-muted and can deliver an output
signal
A slowly rising voltage should be applied (e.g. via an RC network) to pin MODE to ensure
pop noise-free start-up. The bias-current setting of the (VI converter) input stages is
related to the voltage on the MODE pin.
In Mute mode, the bias-current setting of the VI converters is zero (VI converters are
disabled). In Operating mode, the bias current is at a maximum. The time constant
required to apply the DC output offset voltage gradually between Mute and Operating
mode levels can be generated using an RC network connected to pin MODE. An example
of a switching circuit for driving pin MODE is illustrated in Figure 4. If the capacitor was
omitted, the very short switching time constant could result in audible pop noises being
generated at start-up (depending on the DC output offset voltage and loudspeaker used).
Fig 4. Example of mode selection circuit
010aaa552
SGND
mode control
mute/
operating
10 µF
5.6 k
+
5 V
470
standby/
operating
S2S1
5.6 k

TDA8920CTH/N1,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Audio Amplifiers Audio Amp Speaker 1CH Mono/2-CH Stereo
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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