83052I Data Sheet
©2015 Integrated Device Technology, Inc December 15, 201510
INPUTS:
CLK INPUT:
For applications not requiring the use of the test clock, it can be left
oating. Though not required, but for additional protection, a 1kΩ
resistor can be tied from the CLK input to ground.
C
ONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT PINS
APPLICATIONS INFORMATION
83052I Data Sheet
©2015 Integrated Device Technology, Inc December 15, 201511
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS830521I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS830521I is the sum of the core power plus the analog power plus the power dissipated in
the load(s).
The following is the power dissipation for V
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
Core and LVDS Output Power Dissipation
Power (core)
MAX
= V
DD_MAX
* (I
DD
+ I
DDo
) = 3.4565V * (40mA + 5mA) = 155.93mW
Output Impedance R
OUT
Power Dissipation due to Loading 50Ω to V
DD
/2
Output Current I
OUT
= V
DDO_MAX
/ [2 * (50Ω + R
OUT
)] = 3.465 / [2 * (50Ω + 15Ω)] = 26.7mA
Power Dissipation on the R
OUT
per LVCMOS output
Power (R
OUT
) = R
OUT
* (I
OUT
)
2
= 15Ω * (26.7mA)
2
= 10.7mW
Dynamic Power Dissipation at 250MHz
Power (250MHz) = C
PD
* frequency * (V
DD
)
2
= 18pF * 250MHz * (3.465V)
2
= 54.0mW
Total Power Dissipation
Total Power
= Power (core)
MAX
+ Power (R
OUT
) Total Power + Power (250MHz)
= 155.93mW + 10.7mW + 54.0mW
=220.6mW
83052I Data Sheet
©2015 Integrated Device Technology, Inc December 15, 201512
2. Junction Temperature
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of
the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction, TJ, to 125°C
ensures that the bond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θ
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA
must be used. Assuming
no air fl ow and a multi-layer board, the appropriate value is 101.7°C/W per Table 6.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.221W * 101.7°C/W = 107.4°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow,
and the type of board (multi-layer).
TABLE 6. θ
JA
VS. AIR FLOW TABLE FOR 8 LEAD TSSOP
θ
JA
BY Velocity
Meters per Second 0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W

83052AGILFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 2:1 Single Ended MUX
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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