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AMIS42665TJAA1RG

P1-P3P4-P6P7-P9P10-P11
AMIS−42665
http://onsemi.com
4
Table 3. ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Conditions Min. Max. Unit
V
CC
Supply Voltage −0.3 +7 V
V
CANH
DC Voltage at Pin CANH 0 < V
CC
< 5.25 V; No Time Limit −50 +50 V
V
CANL
DC Voltage at Pin CANL 0 < V
CC
< 5.25 V; No Time Limit −50 +50 V
V
SPLIT
DC Voltage at Pin V
SPLIT
0 < V
CC
< 5.25 V; No Time Limit −50 +50 V
V
TxD
DC Voltage at Pin TxD −0.3 V
CC
+ 0.3 V
V
RxD
DC Voltage at Pin RxD −0.3 V
CC
+ 0.3 V
V
STB
DC Voltage at Pin STB −0.3 V
CC
+ 0.3 V
V
tran(CANH)
Transient Voltage at Pin CANH Note 1 −300 +300 V
V
tran(CANL)
Transient voltage at Pin CANL Note 1 −300 +300 V
V
tran(VSPLIT)
Transient Voltage at Pin V
SPLIT
Note 1 −300 +300 V
V
esd(CANL/
CANH/VSPLIT)
Electrostatic Discharge Voltage at CANH and
CANL Pin
Note 2
Note 4
−8
−500
+8
+500
kV
V
V
esd
Electrostatic Discharge Voltage at All Other Pins Note 2
Note 4
−5
−500
+5
+500
kV
V
Latch−up Static Latch−up at all Pins Note 3 120 mA
T
stg
Storage Temperature −55 +150 °C
T
amb
Ambient Temperature −40 +125 °C
T
J
Maximum Junction Temperature −40 +170 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Applied transient waveforms in accordance with ISO 7637 part 3, test pulses 1, 2, 3a, and 3b (see Figure 5).
2. Standardized human body model electrostatic discharge (ESD) pulses in accordance to MIL883 method 3015.7.
3. Static latch−up immunity: Static latch−up protection level when tested according to EIA/JESD78.
4. Standardized charged device model ESD pulses when tested according to EOS/ESD DS5.3−1993.
Table 4. THERMAL CHARACTERISTICS
Symbol Parameter Conditions Value Unit
R
th(vj−a)
Thermal Resistance from Junction−to−Ambient in SOIC−8 Package In free air 145 K/W
R
th(vj−s)
Thermal Resistance from Junction−to−Substrate of Bare Die In free air 45 K/W
FUNCTIONAL DESCRIPTION
AMIS−42665 provides two modes of operation as illustrated in Table 5. These modes are selectable through pin STB.
Table 5. OPERATING MODES
Mode Pin STB
Pin RXD
Low High
Normal Low Bus Dominant Bus Recessive
Standby High Wake−up Request Detected No Wake−up Request Detected
Normal Mode
In the normal mode, the transceiver is able to
communicate via the bus lines. The signals are transmitted
and received to the CAN controller via the pins TxD and
RxD. The slopes on the bus lines outputs are optimized to
give extremely low EME.
Standby Mode
In standby mode both the transmitter and receiver are
disabled and a very low−power differential receiver
monitors the bus lines for CAN bus activity. The bus lines
are terminated to ground and supply current is reduced to a
minimum, typically 10 mA. When a wake−up request is
AMIS−42665
http://onsemi.com
5
detected by the low−power differential receiver, the signal
is first filtered and then verified as a valid wake signal after
a time period of t
dbus
, the RxD pin is driven low by the
transceiver to inform the controller of the wake−up request.
Split Circuit
The V
SPLIT
Pin is operational only in normal mode. In
standby mode this pin is floating. The V
SPLIT
is connected
as shown in Figure 2 and its purpose is to provide a stabilized
DC voltage of 0.5 x V
CC
to the bus avoiding possible steps
in the common−mode signal therefore reducing EME. These
unwanted steps could be caused by an unpowered node on
the network with excessive leakage current from the bus that
shifts the recessive voltage from its nominal 0.5 x V
CC
voltage.
Wake−up
When a valid wake−up (dominant state longer than t
dbus
)
is received during the standby mode the RxD pin is driven
low. Wake−up behavior in case of a permanent dominant –
due to, for example, a bus short – represents the only
difference between the circuit sub−versions listed in the
Ordering Information table. It is depicted in Figures 3 and 4.
When the standby mode is entered while a dominant is
present on the bus, the “unconditioned bus wake−up”
versions will signal a bus−wakeup immediately after the
state transition (seen as a High−level glitch on RxD). The
other version (differing purely by a metal−level
modification in the digital part) will signal bus−wakeup only
after the initial dominant is released. In this way it’s ensured,
that a CAN bus can be put to a low−power mode even if the
nodes have a level sensitivity to RxD pin and a permanent
dominant is present on the bus.
Overtemperature Detection
A thermal protection circuit protects the IC from damage
by switching off the transmitter if the junction temperature
exceeds a value of approximately 160°C. Because the
transmitter dissipates most of the power, the power
dissipation and temperature of the IC are reduced. All other
IC functions continue to operate. The transmitter off−state
resets when Pin TxD goes high. The thermal protection
circuit is particularly needed when a bus line short circuits.
TxD Dominant Time−out Function
A TxD dominant time−out timer circuit prevents the bus
lines being driven to a permanent dominant state (blocking
all network communication) if Pin TxD is forced
permanently low by a hardware and/or software application
failure. The timer is triggered by a negative edge on pin TxD.
If the duration of the low−level on Pin TxD exceeds the
internal timer value t
dom(TxD)
, the transmitter is disabled,
driving the bus into a recessive state. The timer is reset by a
positive edge on Pin TxD. See Figure 10.
This TxD dominant time−out time (t
dom(TxD)
) defines the
minimum possible bit rate to 40 kbps.
Fail Safe Features
A current−limiting circuit protects the transmitter output
stage from damage caused by accidental short circuit to
either positive or negative supply voltage, although power
dissipation increases during this fault condition.
The pins CANH and CANL are protected from
automotive electrical transients (according to ISO 7637; see
Figure 5). Pins TxD and STB are pulled high internally
should the input become disconnected. Pins TxD, STB and
RxD will be floating, preventing reverse supply should the
V
CC
supply be removed.
CANH
CANL
STB
RxD
Normal Standby*
unconditioned WU
Figure 3. AMIS42665TJAA1/3 Wake−up Behavior
time
t
dbus
t
dbus
*Even if bus dominant signals longer than tdbus are echoed on RxD, the transceiver
stays in standby mode until STB is released.
Figure 4. AMIS42665TJAA6 Wake−up Behavior
CANH
CANL
STB
RxD
Normal Standby* time
*On this derivative, bus dominant signals longer than t
dbus
are echoed on RxD after the bus passed through
a recessive time following the trigger of STB. The transceiver stays in standby mode until STB is released.
t
dbus
AMIS−42665
http://onsemi.com
6
ELECTRICAL CHARACTERISTICS
Definitions
All voltages are referenced to GND (Pin 2). Positive
currents flow into the IC.
CHARACTERISTICS V
CC
= 4.75 V to 5.25 V; T
J
= −40°C to +150°C; R
LT
= 60 W unless specified otherwise.
Symbol
Parameter Conditions Min Typ Max Unit
SUPPLY (PIN V
CC
)
I
CC
Supply Current Dominant; V
TxD
= 0 V
Recessive; V
TxD
= V
CC
45
4
65
8
mA
I
CCS
Supply Current in Standby Mode
T
J,max
= 100°C
10 15
mA
TRANSMITTER DATA INPUT (PIN TxD)
V
IH
High−Level Input Voltage Output Recessive 2.0 − V
CC
+
0.3
V
V
IL
Low−Level Input Voltage Output Dominant −0.3 − +0.8 V
I
IH
High−Level Input Current V
TxD
= V
CC
−5 0 +5
mA
I
IL
Low−Level Input Current V
TxD
= 0 V −75 −200 −350
mA
C
i
Input Capacitance Not Tested − 5 10 pF
TRANSMITTER MODE SELECT (PIN STB)
V
IH
High−Level Input Voltage Standby Mode 2.0 − V
CC
+
0.3
V
V
IL
Low−Level Input Voltage Normal Mode −0.3 − +0.8 V
I
IH
High−Level Input Current V
STB
= V
CC
−5 0 +5
mA
I
IL
Low−Level Input Current V
STB
= 0 V −1 −4 −10
mA
C
i
Input Capacitance Not Tested − 5 10 pF
RECEIVER DATA OUTPUT (PIN RxD)
I
oh
High−Level Output Current V
o
= 0.7 x V
CC
−5 −10 −15 mA
I
ol
Low−Level Output Current V
o
= 0.3 x V
CC
5 10 15 mA
BUS LINES (PINS CANH AND CANL)
V
o(reces)
(norm)
Recessive Bus Voltage
Normal Mode
V
TxD
= V
CC
; No Load 2.0 2.5 3.0 V
V
o(reces)
(stby)
Recessive Bus Voltage V
TxD
= V
CC
; No Load
Standby Mode
−100 0 100 mV
I
o(reces)
(CANH)
Recessive Output Current at Pin CANH −35 V < V
CANH
< +35 V;
0 V < V
CC
< 5.25 V
−2.5 − +2.5 mA
I
o(reces)
(CANL)
Recessive Output Current at Pin CANL −35 V < V
CANL
< +35 V;
0 V < V
CC
< 5.25 V
−2.5 − +2.5 mA
I
LI(CANH)
Input Leakage Current to Pin CANH V
CC
= 0 V;
V
CANL
= V
CANH
= 5 V
−10 − +10
mA
I
LI(CANL)
Input Leakage Current to Pin CANL V
CC
= 0 V;
V
CANL
= V
CANH
= 5 V
−10 − +10
mA
V
o(dom)
(CANH)
Dominant Output Voltage at Pin CANH V
TxD
= 0 V 3.0 3.6 4.25 V
V
o(dom)
(CANL)
Dominant Output Voltage at Pin CANL V
TxD
= 0 V 0. 5 1.4 1.75 V
V
o(dif)
(bus_dom)
Differential Bus Output Voltage
(V
CANH
− V
CANL
)
V
TxD
= 0 V; Dominant;
42.5 W < R
LT
< 60 W
1.5 2.25 3.0 V
V
o(dif)
(bus_rec)
Differential Bus Output Voltage
(V
CANH
− V
CANL
)
V
TxD
= V
CC
; Recessive;
No Load
−120 0 +50 mV
I
o(sc)
(CANH)
Short Circuit Output Current at Pin CANH V
CANH
= 0 V; V
TxD
= 0 V −45 −70 −120 mA
P1-P3P4-P6P7-P9P10-P11

AMIS42665TJAA1RG

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Manufacturer:
ON Semiconductor
Description:
CAN Interface IC HS LP CAN TRANSC.
Lifecycle:
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