CORR-8BIT-SC-U2 Datasheet CORR-8BIT-SC-U2, CORR-8BIT-E2-UT2, CORR-8BIT-P2-UT2 | P4-P6

Lattice Semiconductor Correlator IP Core

In this example, two channels and two different coefﬁcient sequences have been conﬁgured. Each channel can be

correlated to either of the two coefﬁcient sequences.

Figure 2. User Interface Timing Diagram for Two-channel Correlator

Figure 3. User Interface Timing Diagram for Two-channel Correlator

The user drives the

irdy

signal high for one clock cycle indicating that the input values are valid. Along with the

input data, the user also sets the

block_start_in

signal. This signal will be taken as a marker by the Correlator

and aligned with the input data as it passes through the Correlator IP core. The next time the

block_start_out

signal is set and

chan_out

= 0, it will indicate that the output data was associated with this input data value. The

block_start

signals act as markers for the user to do frame alignments between the input and outputs of the

Correlator IP core. This is necessary since the core operates on one input data sample at a time. It does not per-

form multiple correlations over “num_lag” values as expressed in Equation 1. This allows the simplest and most

versatile Correlator IP core design. If it is necessary to operate for multiple “lags,” then the user application will

need to add input and output FIFOs around the core to feed data values one sample at time.

At time 178.5µs,

crdy

again goes active indicating that the Correlator IP core is ready to accept the next input

value, and in the example of Figure 2 the user inputs data for channel 1. At time 196.5µs, the correlation result for

channel 0 is ready at the

dout

outputs, and the core outputs a value of 0x9 on

dout

, sets the

chan_out

to 0, and

asserts the

ordy

signal. It also asserts the

block_start_out

signal to indicate that this output value was asso-

ciated with the

din

value from time 175.5µs.

Lattice Semiconductor Correlator IP Core

Figure 4. Tap and Coefﬁcient Memories

Tap and Coefﬁcient Memories

While the Tap and Coefﬁcient Memories are being read, the values read are passed to the Aligner. Under the con-

trol of the state machine the Aligner shifts the tap data and coefﬁcients to be passed to the Correlator block. The

state machine also generates strobe signals to the Aligner which indicate, in any given clock cycle, which tap and

coefﬁcient values are valid for the correlator block to work on.

The Tap and Coefﬁcient Memories are implemented with EBR blocks as shown in Figure 4. The Correlator IP core

will automatically conﬁgure and instantiate the proper number of EBR blocks in the design based on the parame-

ters selected by the user. In the case of the Tap Memory, the number of correlator cells, number of taps, number of

channels, and the oversampling rate all determine how many EBR memories are needed. The number of correlator

cells (parameter MWIDTH) determines how many words of data can be operated on during a single clock cycle.

The more correlator cells which are conﬁgured, the more multiplication operations can occur in a clock cycle and

the overall data throughput goes up. At least one EBR memory is required to feed each correlator cell. All Tap

Memory EBR blocks in the design will be conﬁgured to be at least the word width of the input data (DWIDTH) wide.

The EBR blocks can be sized 1, 2, 4, or 9 bits wide, and must be equal to or greater than DWIDTH. Since each

EBR block can store 8192 bits, if the value of [TAP_EBR_WIDTH * (NUM_TAP / MWIDTH) * NUM_CHAN *

OS_FACTOR] exceeds 8192 bits, then multiple EBR blocks will be stacked in columns to feed the correlator cells,

as shown in Figure 4. TAP_EBR_WIDTH is the minimum allowed EBR width which is at least DWIDTH wide. The

Tap Memory EBRs will be conﬁgured automatically for the user; however, the user is responsible for determining

the total number of EBR blocks needed for the design and insure that the target LatticeEC™ device contains

enough memories.

The Coefﬁcient Memories are also implemented in EBR blocks. Since each coefﬁcient is constrained to be 1 bit,

the total amount of memory required for coefﬁcients is generally less than that required for tap data. Each EBR

EBR Block

Tap Memory

Aligner

Coefficient Memory

Corr

Cell

Corr

Cell

Corr

Cell

Corr

Cell

Number of Correlator

Cells = MWIDTH

Number of Data Words (Taps)

per Row of Memory = MWIDTH

Number of Coefficients

per Row of Memory = MWIDTH

Correlator

EBR BlockEBR Block

EBR BlockEBR BlockEBR Block

Lattice Semiconductor Correlator IP Core

block can be a maximum of 36 bits wide, therefore if the number of correlator cells (MWIDTH) is not greater than

36, only one column of EBR memories is required for the Coefﬁcient Memories. If MWIDTH > 36, then multiple col-

umns will be conﬁgured. As in the case of the Tap Memories, if the total number of coefﬁcients which needs to be

stored exceeds one row of EBR memories, then multiple rows will be conﬁgured in a stacked arrangement as

shown in Figure 4. For MWIDTH

≤

36, the number of coefﬁcients required is [NUM_TAP * NUM_COEF_SEQ]. If

this number is less than 8192 then only one EBR is needed for the Coefﬁcient Memory.

Unlike the Tap Memories which are written with new user data under the control of the state machine, the Coefﬁ-

cient Memories must be written with the coefﬁcient sequences before any correlation operations can be done. This

is done via the Coefﬁcient Memory Conﬁguration interface shown in Figure 5. This interface consists of the input

signals:

coeffaddr

coeffwdat

coeffwdat_im

, and

coeffwr

. Figure 6 shows the timing for this interface for

a two-channel design with MWIDTH=4, NUM_TAP=16 and NUM_COEF_SEQ=2.

Figure 5. Coefﬁcient Memory Conﬁguration Interface Timing

In this case, the Coefﬁcient Memory is implemented in one EBR block. Each row of Coefﬁcient Memory is required

to store MWIDTH=4 coefﬁcients, so each write to the memory writes four bits. Each coefﬁcient sequence is

NUM_TAP=16 bits long, and it will occupy (NUM_TAP / MWIDTH)= 4 rows in the Coefﬁcient Memory. In addition, in

this example there are two separate coefﬁcient sequences, so the coefﬁcients will occupy a total of eight rows in

the Coefﬁcient Memory.

Writes to the Coefﬁcient Memory are enabled by asserting the

coeffwr

input. The

coeffaddr

input selects the

row of memory to be written, and

coeffwdat

(and

coeffwdat_im

for complex correlations) is set to the desired

value. This is a very simple interface, however it is essential to make sure that the coefﬁcient sequence is written in

the correct order. In the example above, the ﬁrst four values written are for coefﬁcient sequence 0. The values writ-

ten are 0xa6fc (or in binary: 1010 0110 1111 1100) with the LSB being the ﬁrst bit in the correlation sequence. This

bit will be multiplied against the newest data value received by the Correlator. The MSB in this string will be multi-

plied against the oldest data read from Tap Memory. This is explained further in the Correlator Evaluation Package

section of this document.

The second coefﬁcient sequence written into the Coefﬁcient Memory is 0x0180, and is written into rows 7, 6, 5 and

4. This will be selected as coefﬁcient sequence 1 by setting the

code_sel_in

to 1 when a data value is input to

the Correlator. Figure 6 shows how the coefﬁcient values from this example would appear in the Coefﬁcient Mem-

ory:

P1-P3 P4-P6 P7-P9 P10-P10

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Development Software Correlator IP Core User Config

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