OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

MC74ACT374DWR2G

P1-P3P4-P6P7-P9P10-P10
Figure 2. Logic Symbol
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CP
OE
© Semiconductor Components Industries, LLC, 2015
March, 2015 − Rev. 9
1 Publication Order Number:
MC74AC374/D
MC74AC374, MC74ACT374
Octal D-Type Flip-Flop with
3-State Outputs
The MC74AC374/74ACT374 is a high−speed, low−power octal
D−type flip−flop featuring separate D−type inputs for each flip−flop
and 3−state outputs for bus−oriented applications. A buffered Clock
(CP) and Output Enable (OE
) are common to all flip−flops.
Features
• Buffered Positive Edge−Triggered Clock
• 3−State Outputs for Bus−Oriented Applications
• Outputs Source/Sink 24 mA
• See MC74AC273 for Reset Version
• See MC74AC377 for Clock Enable Version
• See MC74AC373 for Transparent Latch Version
• See MC74AC574 for Broadside Pinout Version
• See MC74AC564 for Broadside Pinout Version with Inverted
Outputs
• ′ACT374 Has TTL Compatible Inputs
• These are Pb−Free Devices
Figure 1. Pinout: 20 Lead Packages Conductors
(Top View)
1920 18 17 16 15 14
21 34567
V
CC
13
8
12
9
11
10
O
7
D
7
D
6
O
6
O
5
D
5
D
4
O
4
CP
OE
O
0
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
PIN ASSIGNMENT
PIN FUNCTION
D
0
−D
7
Data Inputs
CP Clock Pulse Input
OE 3−State Output Enable Input
O
0
−O
7
3−State Outputs
www.onsemi.com
SOIC−20W
DW SUFFIX
CASE 751D
TSSOP−20
DT SUFFIX
CASE 948E
1
1
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
See general marking information in the device marking
section on page 6 of this data sheet.
DEVICE MARKING INFORMATION
MC74AC374, MC74ACT374
www.onsemi.com
2
TRUTH TABLE
Inputs Outputs
D
n
CP OE O
n
H L H
L L L
X X H Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
FUNCTIONAL DESCRIPTION
The MC74AC374/74ACT374 consists of eight edge−
triggered flip−flops with individual D−type inputs and
3−state true outputs. The buffered clock and buffered Output
Enable are common to all flip−flops. The eight flip−flops
will store the state of their individual D inputs that meet the
setup and hold time requirements on the LOW−to−HIGH
Clock (CP) transition. With the Output Enable (OE
) LOW,
the contents of the eight flip−flops are available at the
outputs. When the OE
is HIGH, the outputs go to the high
impedance state. Operation of the OE
input does not affect
the state of the flip−flops.
Figure 3. Logic Diagram
CP D
QQ
CP D
QQ
CP D
QQ
CP D
QQ
CP D
QQ
CP D
QQ
CP D
QQ
CP D
QQ
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
OE
CP
NOTE: That this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
MC74AC374, MC74ACT374
www.onsemi.com
3
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) −0.5 to +7.0 V
V
IN
DC Input Voltage (Referenced to GND) −0.5 to V
CC
+0.5 V
V
OUT
DC Output Voltage (Referenced to GND) (Note 1) −0.5 to V
CC
+0.5 V
I
IK
DC Input Diode Current ±20 mA
I
OK
DC Output Diode Current ±50 mA
I
OUT
DC Output Sink/Source Current ±50 mA
I
CC
DC Supply Current, per Output Pin ±50 mA
I
GND
DC Ground Current, per Output Pin ±100 mA
T
STG
Storage Temperature Range *65 to )150
_C
T
L
Lead temperature, 1 mm from Case for 10 Seconds 260
_C
T
J
Junction Temperature Under Bias 140
_C
q
JA
Thermal Resistance (Note 2) SOIC
TSSOP
65.8
110.7
_C/W
MSL Moisture Sensitivity Level 1
F
R
Flammability Rating Oxygen Index: 30% − 35% UL 94 V−0 @ 0.125 in
V
ESD
ESD Withstand Voltage Human Body Model (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
> 2000
> 200
> 1000
V
I
Latchup
Latchup Performance Above V
CC
and Below GND at 85_C (Note 6)
±100 mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. I
OUT
absolute maximum rating must be observed.
2. The package thermal impedance is calculated in accordance with JESD 51−7.
3. Tested to EIA/JESD22−A114−A.
4. Tested to EIA/JESD22−A115−A.
5. Tested to JESD22−C101−A.
6. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Typ Max Unit
V
CC
Supply Voltage
′AC 2.0 5.0 6.0
V
′ACT 4.5 5.0 5.5
V
IN
, V
OUT
DC Input Voltage, Output Voltage (Ref. to GND) 0 V
CC
V
t
r
, t
f
Input Rise and Fall Time (Note 1)
′AC Devices except Schmitt Inputs
V
CC
@ 3.0 V − 150 −
V
CC
@ 4.5 V − 40 − ns/V
V
CC
@ 5.5 V − 25 −
t
r
, t
f
Input Rise and Fall Time (Note 2)
′ACT Devices except Schmitt Inputs
V
CC
@ 4.5 V − 10 −
ns/V
V
CC
@ 5.5 V − 8.0 −
T
A
Operating Ambient Temperature Range −40 25 85 °C
I
OH
Output Current − High − − −24 mA
I
OL
Output Current − Low − − 24 mA
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
1. V
IN
from 30% to 70% V
CC
; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. V
IN
from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
P1-P3P4-P6P7-P9P10-P10

MC74ACT374DWR2G

Mfr. #:
Buy MC74ACT374DWR2G
Manufacturer:
ON Semiconductor
Description:
Flip Flops 5V CMOS Octal D-Type 3-State Out
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet