HEF4043B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 15 July 2013 6 of 14
NXP Semiconductors HEF4043B-Q100
Quad R/S latch with 3-state outputs
11. Dynamic characteristics
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (C
L
in pF).
[2] t
t
is the same as t
THL
and t
TLH
.
Table 7. Dynamic characteristics
V
SS
= 0 V; T
amb
= 25
C; For waveforms and test circuit see Section 12; unless otherwise specified.
Symbol Parameter Conditions V
DD
Extrapolation formula Min Typ Max Unit
t
PHL
HIGH to LOW
propagation delay
nR nQ;
see Figure 4
5 V
[1]
63 ns + (0.55 ns/pF)C
L
- 90 180 ns
10 V 24 ns + (0.23 ns/pF)C
L
-3570ns
15 V 17 ns + (0.16 ns/pF)C
L
-2550ns
t
PLH
LOW to HIGH
propagation delay
nS nQ;
see Figure 4
5 V
[1]
38 ns + (0.55 ns/pF)C
L
- 65 135 ns
10 V 14 ns + (0.23 ns/pF)C
L
-2550ns
15 V 7 ns + (0.16 ns/pF)C
L
-1535ns
t
t
transition time nQ output;
see Figure 4
5 V
[1]
[2]
10 ns + (1.00 ns/pF)C
L
- 60 120 ns
10 V 9 ns + (0.42 ns/pF)C
L
-3060ns
15 V 6 ns + (0.28 ns/pF)C
L
-2040ns
t
PHZ
HIGH to OFF-state
propagation delay
OE nQ;
see Figure 5
5 V - 45 90 ns
10 V - 20 35 ns
15 V - 10 25 ns
t
PLZ
LOW to OFF-state
propagation delay
OE nQ;
see Figure 5
5 V - 50 100 ns
10 V - 20 40 ns
15 V - 10 25 ns
t
PZH
OFF-state to HIGH
propagation delay
OE nQ;
see Figure 5
5 V - 25 50 ns
10 V - 15 30 ns
15 V - 10 25 ns
t
PZL
OFF-state to LOW
propagation delay
OE nQ;
see Figure 5
5 V - 40 80 ns
10 V - 20 45 ns
15 V - 15 35 ns
t
W
pulse width nS input HIGH;
minimum width;
see Figure 4
5 V 30 15 - ns
10 V 20 10 - ns
15 V 16 8 - ns
nR input HIGH;
minimum width;
see Figure 4
5 V 30 15 - ns
10 V 20 10 - ns
15 V 16 8 - ns
HEF4043B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 15 July 2013 7 of 14
NXP Semiconductors HEF4043B-Q100
Quad R/S latch with 3-state outputs
12. Waveforms
Table 8. Dynamic power dissipation P
D
P
D
can be calculated from the formulas shown. V
SS
= 0 V; t
r
= t
f
20 ns; T
amb
= 25
C.
Symbol Parameter V
DD
Typical formula for P
D
(W) where:
P
D
dynamic power
dissipation
5 V P
D
= 1100 f
i
+ (f
o
C
L
) V
DD
2
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
DD
= supply voltage in V;
(f
o
C
L
) = sum of the outputs.
10 V P
D
= 4400 f
i
+ (f
o
C
L
) V
DD
2
15 V P
D
= 11400 f
i
+ (f
o
C
L
) V
DD
2
t
r
and t
f
are the input rise and fall times.
Logic levels: V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Transition times: transition time (t
t
) = HIGH LOW (t
THL
) or LOW HIGH (t
TLH
) transition times.
Measurement points are given in Table 9
and test data is given in Table 10.
Fig 4. Input minimum set (nS) and reset (nR) pulse widths, inputs nS or nR to latch output (nQ) propagation
delay and nQ transition time
001aai286
input nR
output nQ
t
PHL
t
PLH
0 V
V
I
V
M
V
OH
V
OL
t
THL
t
TLH
input nS
0 V
V
I
V
M
V
M
t
W
t
W
10 %
10 %
90 %
90 %
t
r
t
f
HEF4043B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 15 July 2013 8 of 14
NXP Semiconductors HEF4043B-Q100
Quad R/S latch with 3-state outputs
Measurement points are given in Table 9.
Fig 5. Output enable (OE) to latch output (nQ) enable time (t
PZL
and t
PZH
) and disable time (t
PLZ
and t
PHZ
)
001aag355
t
PLZ
t
PHZ
outputs off outputs onoutputs on
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
OE input
V
DD
V
DD
V
SS
V
SS
V
DD
V
SS
t
PZL
t
PZH
V
Y
V
Y
V
X
V
X
Table 9. Measurement points
Supply voltage Input Output
V
DD
V
I
V
M
V
M
V
X
V
Y
5 V to 15 V V
DD
or 0 V 0.5V
DD
0.5V
DD
0.1V
DD
0.9V
DD

HEF4043BT-Q100J

Mfr. #:
Manufacturer:
Nexperia
Description:
Latches Quad R/S latch with outputs
Lifecycle:
New from this manufacturer.
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