MC74HC175ADTR2

Semiconductor Components Industries, LLC, 1999
March, 2000 – Rev. 2
1 Publication Order Number:
MC74HC175A/D
High–Performance Silicon–Gate CMOS
The MC74HC175A is identical in pinout to the LS175. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of four D flip–flops with common Reset and
Clock inputs, and separate D inputs. Reset (active–low) is
asynchronous and occurs when a low level is applied to the Reset
input. Information at a D input is transferred to the corresponding Q
output on the next positive going edge of the Clock input.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity 166 FETs or 41.5 Equivalent Gates
LOGIC DIAGRAM
PIN 16 = V
CC
PIN 8 = GND
9
4
5
12
13
CLOCK
D0
D1
D2
D3
RESET
1
DATA
INPUTS
2
3
7
6
10
11
15
14
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
INVERTING
AND
NONINVERTING
OUTPUTS
FUNCTION TABLE
Inputs Outputs
Reset Clock D Q Q
LXXLH
HHHL
HLLH
H L X No Change
SO–16
D SUFFIX
CASE 751B
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TSSOP–16
DT SUFFIX
CASE 948F
1
16
PDIP–16
N SUFFIX
CASE 648
1
16
1
16
MARKING
DIAGRAMS
1
16
MC74HC175AN
AWLYYWW
1
16
HC175A
AWLYWW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
HC
175A
ALYW
1
16
Device Package Shipping
ORDERING INFORMATION
MC74HC175AN PDIP–16 2000 / Box
MC74HC175AD SOIC–16
48 / Rail
MC74HC175ADR2 SOIC–16 2500 / Reel
MC74HC175ADT TSSOP–16 96 / Rail
MC74HC175ADTR2 TSSOP–16
2500 / Reel
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
D2
D3
Q3
Q3
V
CC
CLOCK
Q2
Q2
D0
Q0
Q0
RESET
GND
Q1
Q1
D1
MC74HC175A
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2
MAXIMUM RATINGS*
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V
V
in
DC Input Voltage (Referenced to GND) – 0.5 to V
CC
+ 0.5 V
V
out
DC Output Voltage (Referenced to GND) – 0.5 to V
CC
+ 0.5 V
I
in
DC Input Current, per Pin ± 20 mA
I
out
DC Output Current, per Pin ± 25 mA
I
CC
DC Supply Current, V
CC
and GND Pins ± 50 mA
P
D
Power Dissipation in Still Air, Plastic DIP†
SOIC Package†
TSSOP Package†
750
500
450
mW
T
stg
Storage Temperature – 65 to + 150
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
260
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: – 10 mW/ C from 65 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
TSSOP Package: – 6.1 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage (Referenced to GND) 2.0 6.0 V
V
in
, V
out
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
CC
V
T
A
Operating Temperature, All Package Types – 55 + 125
C
t
r
, t
f
Input Rise and Fall Time V
CC
= 2.0 V
(Figure 1) V
CC
= 3.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
0
0
0
1000
600
500
400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol Parameter Test Conditions
V
CC
V
– 55 to
25 C
85 C 125 C
Unit
V
IH
Minimum High–Level Input
Voltage
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
| 20 µA
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4 2
V
V
IL
Maximum Low–Level Input
Voltage
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
| 20 µA
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.80
0.5
0.9
1.35
1.80
0.5
0.9
1.35
1.80
V
V
OH
Minimum High–Level Output
Voltage
V
in
= V
IH
or V
IL
|I
out
| 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
in
= V
IH
or V
IL
|I
out
| 2.4 mA
|I
out
| 4.0 mA
|I
out
| 5.2 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND (V
in
or V
out
) V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
MC74HC175A
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3
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Unit
Guaranteed Limit
V
CC
V
Test ConditionsParameterSymbol Unit
125 C 85 C
– 55 to
25 C
V
CC
V
Test ConditionsParameterSymbol
V
OL
Maximum Low–Level Output
Voltage
V
in
= V
IH
or V
IL
|I
out
| 20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IH
or V
IL
|I
out
| 2.4 mA
|I
out
| 4.0 mA
|I
out
| 5.2 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
I
in
Maximum Input Leakage
Current
V
in
= V
CC
or GND 6.0 ± 0.1 ± 1.0 ± 1.0 µA
I
CC
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
I
out
= 0 µA
6.0 4 40 160 µA
NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Guaranteed Limit
Symbol Parameter
V
CC
V
– 55 to
25 C
85 C 125 C
Unit
f
max
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
3.0
4.5
6.0
6
10
30
35
4.8
8.0
24
28
4
6
20
24
MHz
t
PLH
,
t
PHL
Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
2.0
3.0
4.5
6.0
150
75
26
22
190
90
32
28
225
110
38
33
ns
t
PHL
Maximum Propagation Delay, Reset to Q or Q
(Figures 2 and 4)
2.0
3.0
4.5
6.0
125
70
22
19
155
85
27
24
190
110
34
30
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
C
in
Maximum Input Capacitance 10 10 10 pF
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance (Per Flip–Flop)*
35
pF
* Used to determine the no–load dynamic power consumption: P
D
= C
PD
V
CC
2
f + I
CC
V
CC
. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).

MC74HC175ADTR2

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Flip Flops 2-6V CMOS Quad
Lifecycle:
New from this manufacturer.
Delivery:
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