Document Number: 001-73555 Rev. *B Page 8 of 19
Serial Bus Programming Protocol and Timing
The CY22393 has a 2-wire serial interface for in-system
programming. They use the SDAT and SCLK pins, and operate
up to 400 kbit/s in Read or Write mode. Except for the data hold
time, it is compliant with the I
2
C bus standard. The basic Write
serial format is as follows:
Start Bit; 7-bit Device Address (DA); R/W
Bit; Slave Clock
Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit
Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in
MA+2; ACK; etc. until STOP Bit.
The basic serial format is illustrated in Figure 3 on page 9.
Default Startup Condition for the CY22393
The default (programmed) condition of CY24293 is set by the
distributor, who programs the device using a customer-specified
JEDEC file produced by CyClocksRT, Cypress’s proprietary
development software. Parts shipped by the factory are blank
and unprogrammed. In this condition, all bits are set to 0, all
outputs are tristated, and the crystal oscillator circuit is active.
While users can develop their own subroutine to program any or
all of the individual registers as described in the following pages,
it may be easier to simply use CyClocksRT to produce the
required register setting file.
Device Address
The device address is a 7-bit value that is configured during Field
Programming. By programming different device addresses, two
or more parts are connected to the serial interface and can be
independently controlled. The device address is combined with
a read/write bit as the LSB and is sent after each start bit.
The default serial interface address is 69H, but there must not
be a conflict with any other devices in your system. This can also
be changed using CyClocksRT.
Data Valid
Data is valid when the clock is HIGH, and can only be
transitioned when the clock is LOW as illustrated in Figure 4 on
page 9.
Data Frame
Every new data frame is indicated by a start and stop sequence,
as illustrated in Figure 5 on page 10.
Start Sequence - Start Frame is indicated by SDAT going LOW
when SCLK is HIGH. Every time a start signal is given, the next
8-bit data must be the device address (seven bits) and a R/W
bit,
followed by the register address (eight bits) and register data
(eight bits).
Stop Sequence - Stop Frame is indicated by SDAT going HIGH
when SCLK is HIGH. A Stop Frame frees the bus for writing to
another part on the same bus or writing to another random
register address.
Acknowledge Pulse
During Write Mode, the CY22393 responds with an
Acknowledge pulse after every eight bits. To do this, it pulls the
SDAT line LOW during the N*9
th
clock cycle, as illustrated in
Figure 6 on page 10. (N = the number of bytes transmitted).
During Read Mode, the master generates the acknowledge
pulse after the data packet is read.
Write Operations
Writing Individual Bytes
A valid write operation must have a full 8-bit register address
after the device address word from the master, which is followed
by an acknowledge bit from the slave (ack = 0/LOW). The next
eight bits must contain the data word intended for storage. After
the data word is received, the slave responds with another
acknowledge bit (ack = 0/LOW), and the master must end the
write sequence with a STOP condition.
Writing Multiple Bytes
To write multiple bytes at a time, the master must not end the
write sequence with a STOP condition. Instead, the master
sends multiple contiguous bytes of data to be stored. After each
byte, the slave responds with an acknowledge bit, the same as
after the first byte, and accepts data until the STOP condition
responds to the acknowledge bit. When receiving multiple bytes,
the CY22393 internally increment the register address.
Read Operations
Read operations are initiated the same way as Write operations
except that the R/W bit of the slave address is set to ‘1’ (HIGH).
There are three basic read operations: current address read,
random read, and sequential read.
Current Address Read
The CY22393 have an onboard address counter that retains “1”
more than the address of the last word access. If the last word
written or read was word ‘n’, then a current address read
operation returns the value stored in location ‘n+1’. When the
CY22393 receives the slave address with the R/W bit set to a ‘1’,
it issues an acknowledge and transmit the 8-bit word. The master
device does not acknowledge the transfer, but generates a
STOP condition, which causes the CY22393 to stop
transmission.
Random Read
Through random read operations, the master may access any
memory location. To perform this type of read operation, first set
the word address. Do this by sending the address to the
CY22393 as part of a write operation. After the word address is
sent, the master generates a START condition following the
acknowledge. This terminates the write operation before any
data is stored in the address, but not before setting the internal
address pointer. Next, the master reissues the control byte with
the R/W byte set to ‘1’. The CY22393, then, issues an
acknowledge and transmits the 8-bit word. The master device
does not acknowledge the transfer, but generates a STOP
condition which causes CY22393 to stop transmission.
Sequential Read
Sequential read operations follow the same process as random
reads except that the master issues an acknowledge instead of
a STOP condition after transmitting the first 8-bit data word. This
action increments the internal address pointer, and subsequently
outputs the next 8-bit data word. By continuing to issue
