QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1294A
ADJUSTABLE LDO LINEAR REGULATORS IN PARALLEL
4
BYPASS CAPACITOR
Since the SET pin is a high impedance node, unwanted
signals may couple into the SET pin and cause erratic
behavior. This will be most noticeable when operating
with minimum output capacitors at full load current.
The easiest way to remedy this is to bypass the SET
pin with a small amount of capacitance from SET to
ground, 10pF to 20pF is sufficient. A 0.01uF bypass
capacitor is used on the demo board to provide a low-
noise output. Please refer to datasheet for details.
PARALLEL OPERATION
A small ballast resistor is required for parallel opera-
tion, such as 20m
. A short PCB trace can easily
serve that purpose. Refer to the datasheet for trace
length calculation.
THE BOTTOM PAD OF IC IS THE
OUTPUT
. The bottom pad can be tied to the output pin
respectively, however, each bottom pad should iso-
lated from the others, thus force the output current go
through the ballast resistors.
