9
LT1424-9
sn14249 14249fs
OPERATION
U
Combination with the previous V
FLBK
expression yields an
expression for V
OUT
, in terms of the internal reference,
programming resistors, transformer turns ratio and diode
forward voltage drop:
V
OUT
= V
BG
– V
F
– I
SEC
(ESR)
R
FB
R
REF
)
)
N
SP
α
)
)
Additionally, it includes the effect of nonzero secondary
output impedance. See Load Compensation for details.
The practical aspects of applying this equation for V
OUT
are
found in the Applications Information section.
So far, this has been a pseudo-DC treatment of flyback
error amplifier operation. But the flyback signal is a pulse,
not a DC level. Provision must be made to enable the
flyback amplifier only when the flyback pulse is present.
This is accomplished by the dashed line connections to the
block labeled “ENABLE”. Timing signals are then required
to enable and disable the flyback amplifier.
ERROR AMPLIFIER—DYNAMIC THEORY
There are several timing signals that are required for
proper LT1424-9 operation. Please refer to the Timing
Diagram.
Minimum Output Switch ON Time
The LT1424-9 effects output voltage regulation via flyback
pulse action. If the output switch is not turned on at all,
there will be no flyback pulse, and output voltage informa-
tion is no longer available. This would cause irregular loop
response and start-up/latchup problems. The solution
chosen is to require the output switch to be on for an
absolute minimum time per each oscillator cycle. This in
turn establishes a minimum load requirement to maintain
regulation. See Applications Information section for fur-
ther details.
Enable Delay
When the output switch shuts off, the flyback pulse
appears. However, it takes a finite time until the trans-
former primary side voltage waveform approximately rep-
resents the output voltage. This is partly due to rise time
on the V
SW
node, but more importantly due to transformer
leakage inductance. The latter causes a voltage spike on
the primary side not directly related to output voltage.
(Some time is also required for internal settling of the
feedback amplifier circuitry.)
In order to maintain immunity to these phenomena, a fixed
delay is introduced between the switch turn-off command
and the enabling of the feedback amplifier. This is termed
“enable delay”. In certain cases where the leakage spike is
not sufficiently settled by the end of the enable delay
period, regulation error may result. See Applications
Information section for further details.
Collapse Detect
Once the feedback amplifier is enabled, some mechanism
is then required to disable it. This is accomplished by a
collapse detect comparator, that compares the flyback
voltage (R
REF
referred) to a fixed reference, nominally
80% of V
BG
. When the flyback waveform drops below this
level, the feedback amplifier is disabled. This action
accommodates both continuous and discontinuous mode
operation.
Minimum Enable Time
The feedback amplifier, once enabled, stays enabled for a
fixed minimum time period termed “minimum enable
time”. This prevents lock-up, especially when the output
voltage is abnormally low, e.g., during start-up. The mini-
mum enable time period ensures that the V
C
node is able
to “pump up” and increase the current mode trip point to
the level where the collapse detect system exhibits proper
operation. The “minimum enable time” often determines
the low load level at which output voltage regulation is lost.
See Applications Information section for details.
Effects of Variable Enable Period
It should now be clear that the flyback amplifier is enabled
only during a portion of the cycle time. This can vary from
the fixed “minimum enable time” described to a maximum
of roughly the OFF switch time minus the enable delay
