LT6550/LT6551
10
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LT6550 Block Diagram
BLOCK DIAGRA S
W
+
V
CC
OA
450 450
+
OA
450 450
+
OA
450 450
IN1
IN2
IN3
GND
V
EE
OUT1
OUT2
OUT3
N/C
6550 BD01
+
V
CC
OA
450 450
+
OA
450 450
+
OA
450 450
IN1
IN2
IN3
IN4
GND
OUT1
OUT2
OUT3
OUT4
6551 BD02
+
OA
450 450
LT6551 Block Diagram
LT6550/LT6551
11
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APPLICATIO S I FOR ATIO
WUU
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Amplifier Characteristics
Figure 1 shows a simplified schematic of one channel of
the LT6551 quad. Resistors RF and RG provide an internal
gain of 2. (The LT6550 triple is a slight variation with the
gain setting resistor, RG, connected to a separate ground
pin). The input stage consists of transistors Q1 to Q8 and
resistor R1. This topology allows for high slew rates at low
supply voltages. There are back-to-back series diodes, D1
to D4, across the + and – inputs of each amplifier to limit
the differential input voltage to ±1.4V. R
IN
limits the
current through these diodes if the input differential volt-
age exceeds ±1.4V. The input stage drives the degenera-
tion resistors of PNP and NPN current mirrors, Q9 to Q12,
that convert the differential signals into a single-ended
output. The complementary drive generator supplies cur-
rent to the output transistors that swing from rail-to-rail.
Input Voltage Range
The input voltage range is V
EE
to (V
CC
– 1.75V) over
temperature. If the device is operated on a single 3V supply
Figure 1. LT6551 Simplified Schematic
the maximum input is (3V – 1.75V) or 1.25V, and the
internal gain of two will set the output voltage to 2.5V.
Increasing the input beyond 1.25V will force the device out
of its linear range, no longer a gain of 2, and the output will
not increase beyond 2.5V. At a higher supply voltage, i.e.
5V, the maximum input voltage is 5V – 1.75V or 3.25V.
However, due to the internal gain of 2, the output will clip
with a lower input voltage. For linear unclipped operation
the minimum input voltage is (V
OUT
Min)/2 and the maxi-
mum input voltage is (V
OUT
Max)/2 or (V
CC
– 1.75V),
whichever is less.
ESD
The LT6550/LT6551 have reverse-biased ESD protection
diodes on all inputs and outputs as shown in Figure 1. If
these pins are forced beyond either supply, unlimited
current will flow through these diodes. If the current is
limited to 10mA or less, no damage to the device will
occur.
COMPLEMENTARY
DRIVE
GENERATOR
6551 F01
OUT
V
+
GND
DESD3
DESD4
DESD1
DESD2
IN
D3
D4
D1
D2
I1 I2 I3
I4
Q1
Q2
Q3
Q4
Q5
Q10
Q13
Q9
Q12
Q14
Q11
Q6
Q7
Q8
R
IN
225
RG
450
RF
450
R1
R2 R3
R4 R5
CM
V
+
GND
V
+
GND
+–
LT6550/LT6551
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Power Dissipation
The LT6550/LT6551, enhanced θ
JA
MS package, has
Pin 5 (V
EE
for the LT6550 and GND for the LT6551) fused
to the lead frame. This thermal connection increases the
efficiency of the PC board as a heat sink. The PCB material
can be very effective at transmitting heat between the pad
area attached to Pin 5 and a ground or power plane layer.
Copper board stiffeners and plated through holes can also
be used to spread the heat generated by the device. Table 1
lists the thermal resistance for several different board
sizes and copper areas. All measurements were taken on
3/32” FR-4 board with 2oz copper. This data can be used
as a rough guideline in estimating thermal resistance. The
thermal resistance for each application will be affected by
thermal interactions with other components as well as
board size and shape.
Table 1. Fused 10-Lead MSOP Package
COPPER AREA
TOPSIDE* BACKSIDE BOARD AREA THERMAL RESISTANCE
(mm2) (mm2) (mm2) (JUNTION-TO-AMBIENT)
540 540 2500 110°C/W
100 100 2500 120°C/W
100 0 2500 130°C/W
30 0 2500 135°C/W
0 0 2500 140°C/W
*Device is mounted on topside.
As an example, calculate the junction temperature for the
circuit in Figure 2 assuming an 85°C ambient temperature.
The device dissipation can be found by measuring the
supply current, calculating the total dissipation and then
subtracting the dissipation in the load.
The dissipation for the amplifiers is:
P
D
= (106mA)(5V) –4 • (2.5V)
2
/150 = 363mW
The total package power dissipation is 363mW. When a
2500 sq mm PC board with 540 sq mm of 2oz copper on
top and bottom is used, the thermal resistance is
110°C/W. The junction temperature (T
J
) is:
T
J
= (363mW)(110°C/W) + 85°C = 125°C
The maximum junction temperature for the LT6551 is
150°C so the heat sinking capability of the board is
adequate for the application.
Figure 2. Calculating Junction Temperature
+
5V
1.25V
OA
450 450
+
OA
450 450
+
OA
450 450
+
GND
OA
450 450
75
75
75
75
75
75
75
75
LT6551
6551 F02
APPLICATIO S I FOR ATIO
WUU
U

LT6551IMS#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Video Amplifiers 3.3V Quad 110MHz Video buffer
Lifecycle:
New from this manufacturer.
Delivery:
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