Document Number: 38-07012 Rev. *K Page 7 of 14
Switching Characteristics
Parameter Description Conditions Min Typ Max Unit
1/t
1
Output frequency
[4, 5]
Clock output limit, commercial – – 200 MHz
Clock output limit, industrial – – 166 MHz
t
2
Output duty cycle
[4, 6]
Duty cycle for outputs, defined as
t
2
t
1
, Fout < 100 MHz,
divider >= 2, measured at V
DD
/2
45% 50% 55%
Duty cycle for outputs, defined as
t
2
t
1
, Fout > 100 MHz or
divider = 1, measured at V
DD
/2
40% 50% 60%
t
3
Rising edge slew rate
[4]
Output clock rise time, 20% to 80%
of V
DD
0.75 1.4 – V/ns
t
4
Falling edge slew rate
[4]
Output clock fall time, 20% to 80%
of V
DD
0.75 1.4 – V/ns
t
5
Output three-state timing
[4]
Time for output to enter or leave
three-state mode after
SHUTDOWN/OE switches
– 150 300 ns
t
6
Clock jitter
[4, 7]
Peak-to-peak period jitter, CLK
outputs measured at V
DD
/2
– 200 – ps
t
7
Lock time
[4]
PLL Lock Time from Power up – 1.0 3 ms
Notes
4. Guaranteed by design, not 100% tested.
5. Guaranteed to meet 20%–80% output thresholds and duty cycle specifications.
6. Reference Output duty cycle depends on XTALIN duty cycle.
7. Jitter varies significantly with configuration. Reference Output jitter depends on XTALIN jitter and edge rate.
