74LVC823A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 8 April 2013 9 of 21
NXP Semiconductors
74LVC823A
9-bit D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
t
dis
disable time OE to Qn; see Figure 10
[2]
V
CC
= 1.2 V - 8.0 - - - ns
V
CC
= 1.65 V to 1.95 V 2.3 4.2 10.0 2.3 11.5 ns
V
CC
= 2.3 V to 2.7 V 1.0 2.3 5.6 1.0 6.5 ns
V
CC
= 2.7 V 1.5 3.2 7.1 1.5 9.0 ns
V
CC
= 3.0 V to 3.6 V 1.5 2.9 6.0 1.5 7.5 ns
t
W
pulse width clock HIGH or LOW; see Figure 7
V
CC
= 1.65 V to 1.95 V 5.0 - - 5.0 - ns
V
CC
= 2.3 V to 2.7 V 4.0 - - 4.0 - ns
V
CC
=2.7V 3.3 - - 3.3 - ns
V
CC
= 3.0 V to 3.6 V 3.3 1.7 - 3.3 - ns
master reset HIGH or LOW;
see Figure 9
V
CC
= 1.65 V to 1.95 V 5.0 - - 5.0 - ns
V
CC
= 2.3 V to 2.7 V 4.0 - - 4.0 - ns
V
CC
=2.7V 3.3 - - 3.3 - ns
V
CC
= 3.0 V to 3.6 V 3.3 1.7 - 3.3 - ns
t
su
set-up time Dn to CP; see Figure 8
V
CC
= 1.65 V to 1.95 V 3.0 - - 3.0 - ns
V
CC
= 2.3 V to 2.7 V 2.0 - - 2.0 - ns
V
CC
=2.7V 1.0 - - 1.0 - ns
V
CC
= 3.0 V to 3.6 V +1.8 0.8 - +1.8 - ns
CE
to CP; see Figure 8
V
CC
= 1.65 V to 1.95 V 3.0 - - 3.0 - ns
V
CC
= 2.3 V to 2.7 V 2.0 - - 2.0 - ns
V
CC
=2.7V 1.8 - - 1.8 - ns
V
CC
= 3.0 V to 3.6 V 1.3 0.0 - 1.3 - ns
t
rec
recovery time MR; see Figure 9
V
CC
= 1.65 V to 1.95 V 3.0 - - 3.0 - ns
V
CC
= 2.3 V to 2.7 V 2.5 - - 2.5 - ns
V
CC
=2.7V 2.0 - - 2.0 - ns
V
CC
= 3.0 V to 3.6 V +1.0 0.5 - +1.0 - ns
Table 7. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 11.
Symbol Parameter Conditions T
amb
= 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
74LVC823A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 8 April 2013 10 of 21
NXP Semiconductors
74LVC823A
9-bit D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
[1] Typical values are measured at T
amb
=25C and V
CC
= 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.
[2] t
pd
is the same as t
PLH
and t
PHL
.
t
en
is the same as t
PZL
and t
PZH
.
t
dis
is the same as t
PLZ
and t
PHZ
.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz; f
o
= output frequency in MHz
C
L
= output load capacitance in pF
V
CC
= supply voltage in Volts
N = number of inputs switching
(C
L
V
CC
2
f
o
) = sum of the outputs
t
h
hold time Dn to CP; see Figure 8
V
CC
= 1.65 V to 1.95 V 3.0 - - 3.0 - ns
V
CC
= 2.3 V to 2.7 V 2.5 - - 2.5 - ns
V
CC
=2.7V 2.0 - - 2.0 - ns
V
CC
= 3.0 V to 3.6 V 2.0 0.8 - 2.0 - ns
CE
to CP; see Figure 8
V
CC
= 1.65 V to 1.95 V 3.0 - - 3.0 - ns
V
CC
= 2.3 V to 2.7 V 2.0 - - 2.0 - ns
V
CC
=2.7V 1.3 - - 1.3 - ns
V
CC
= 3.0 V to 3.6 V 1.3 0.0 - 1.3 - ns
f
max
maximum
frequency
see Figure 7
V
CC
= 1.65 V to 1.95 V 100 - - 80 - MHz
V
CC
= 2.3 V to 2.7 V 125 - - 100 - MHz
V
CC
= 2.7 V 150 - - 120 - MHz
V
CC
= 3.0 V to 3.6 V 150 200 - 120 - MHz
t
sk(o)
output skew
time
V
CC
= 3.0 V to 3.6 V
[3]
- - 1.0 - 1.5 ns
C
PD
power
dissipation
capacitance
per input; V
I
=GNDtoV
CC
[4]
V
CC
= 1.65 V to 1.95 V - 12.4 - - - pF
V
CC
= 2.3 V to 2.7 V - 14.5 - - - pF
V
CC
= 3.0 V to 3.6 V - 16.4 - - - pF
Table 7. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 11.
Symbol Parameter Conditions T
amb
= 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
74LVC823A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 8 April 2013 11 of 21
NXP Semiconductors
74LVC823A
9-bit D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
11. Waveforms
Measurement points are given in Table 8.
V
OL
and V
OH
are the typical output voltage levels that occur with the output load.
Fig 7. Clock to output propagation delays, clock pulse width, and maximum frequency
mna894
CP
input
Qn
output
t
PHL
t
PLH
t
W
1/f
max
V
M
V
OH
V
I
GND
V
OL
V
M
Measurement points are given in Table 8.
V
OL
and V
OH
are the typical output voltage levels that occur with the output load.
The shaded areas indicate when the input is permitted to change for predicable output performance.
Fig 8. Data set-up and hold times for data and clock enable inputs to clock input
001aaa851
GND
GND
t
h
t
su
t
h
t
su
V
M
V
M
V
M
V
I
V
OH
V
OL
V
I
Qn output
CP input
Dn, CE input

74LVC823AD,118

Mfr. #:
Manufacturer:
Nexperia
Description:
Flip Flops 9BIT BUS INTERFACE
Lifecycle:
New from this manufacturer.
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