MC14027BD

Semiconductor Components Industries, LLC, 2000
August, 2000 – Rev. 4
1 Publication Order Number:
MC14027B/D
MC14027B
Dual J-K Flip-Flop
The MC14027B dual J–K flip–flop has independent J, K, Clock (C),
Set (S) and Reset (R) inputs for each flip–flop. These devices may be
used in control, register, or toggle functions.
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic Swing Independent of Fanout
Logic Edge–Clocked Flip–Flop Design —
Logic state is retained indefinitely with clock level either high or low;
information is transferred to the output only on the positive–going
edge of the clock pulse
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
Pin–for–Pin Replacement for CD4027B
MAXIMUM RATINGS (Voltages Referenced to V
SS
) (Note 2.)
Symbol
Parameter Value Unit
V
DD
DC Supply Voltage Range –0.5 to +18.0 V
V
in
, V
out
Input or Output Voltage Range
(DC or Transient)
–0.5 to V
DD
+ 0.5 V
I
in
, I
out
Input or Output Current
(DC or Transient) per Pin
±10 mA
P
D
Power Dissipation,
per Package (Note 3.)
500 mW
T
A
Ambient Temperature Range –55 to +125 °C
T
stg
Storage Temperature Range –65 to +150 °C
T
L
Lead Temperature
(8–Second Soldering)
260 °C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/C From 65C To 125C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
(V
in
or V
out
) V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
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A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
Device Package Shipping
ORDERING INFORMATION
MC14027BCP PDIP–16 2000/Box
MC14027BD SOIC–16 2400/Box
MC14027BDR2 SOIC–16 2500/Tape & Reel
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
MARKING
DIAGRAMS
1
16
PDIP–16
P SUFFIX
CASE 648
MC14027BCP
AWLYYWW
SOIC–16
D SUFFIX
CASE 751B
1
16
14027B
AWLYWW
SOEIAJ–16
F SUFFIX
CASE 966
1
16
MC14027B
ALYW
MC14027BF SOEIAJ–16 See Note 1.
MC14027BFEL SOEIAJ–16 See Note 1.
MC14027B
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2
TRUTH TABLE
Inputs Outputs*
C
J K S R Q
n
Q
n+1
Q
n+1
1 X 0 0 0 1 0
X 0 0 0 1 1 0
0 X 0 0 0 0 1
X 1 0 0 1 0 1
1 1 0 0 Qo Qo Qo
X X 0 0 X Q
n
Q
n
X X X 1 0 X 1 0
X X X 0 1 X 0 1
X X X 1 1 X 1 1
X = Don’t Care
= Present State
= Level Change * = Next State
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
R
B
C
B
Q
B
Q
B
V
DD
S
B
J
B
K
B
R
A
C
A
Q
A
Q
A
V
SS
S
A
J
A
K
A
PIN ASSIGNMENT
BLOCK DIAGRAM
12
11
13
10
9
4
5
3
6
7
14
15
2
1
S
S
R
R
K
C
J
K
C
JQ
Q
Q
Q
V
DD
= PIN 16
V
SS
= PIN 8
No
Change
MC14027B
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3
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
)
V
DD
– 55C 25C 125C
Characteristic Symbol
V
DD
Vdc
Min Max Min Typ
(4.)
Max Min Max
Unit
Output Voltage “0” Level
V
in
= V
DD
or 0
V
OL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
V
in
= 0 or V
DD
“1” Level
V
OH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage “0” Level
(V
O
= 4.5 or 0.5 Vdc)
(V
O
= 9.0 or 1.0 Vdc)
(V
O
= 13.5 or 1.5 Vdc)
V
IL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
Vdc
(V
O
= 0.5 or 4.5 Vdc) “1” Level
(V
O
= 1.0 or 9.0 Vdc)
(V
O
= 1.5 or 13.5 Vdc)
V
IH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
Vdc
Output Drive Current
(V
OH
= 2.5 Vdc) Source
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
I
OH
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
– 1.7
– 0.36
– 0.9
– 2.4
mAdc
(V
OL
= 0.4 Vdc) Sink
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current I
in
15 ± 0.1 ±0.00001 ± 0.1 ± 1.0 µAdc
Input Capacitance
(V
in
= 0)
C
in
5.0 7.5 pF
Quiescent Current
(Per Package)
I
DD
5.0
10
15
1.0
2.0
4.0
0.002
0.004
0.006
1.0
2.0
4.0
30
60
120
µAdc
Total Supply Current
(5.)
(6.)
(Dynamic plus Quiescent,
Per Package)
(C
L
= 50 pF on all outputs, all
buffers switching)
I
T
5.0
10
15
I
T
= (0.8 µA/kHz) f + I
DD
I
T
= (1.6 µA/kHz) f + I
DD
I
T
= (2.4 µA/kHz) f + I
DD
µAdc
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at 25C.
6. To calculate total supply current at loads other than 50 pF:
I
T
(C
L
) = I
T
(50 pF) + (C
L
– 50) Vfk
where: I
T
is in µA (per package), C
L
in pF, V = (V
DD
– V
SS
) in volts, f in kHz is input frequency, and k = 0.002.

MC14027BD

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Flip Flops 3-18V CMOS Dual
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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