IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
8
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage
(5)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. The specification for t
DH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual t
DH will always be smaller than the actual tOW.
4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read”.
5. 'X' in part number indicates power rating (SA or LA).
Symbol Parameter
7134X20
Com'l Only
7134X25
Com'l & Ind
7134X35
Com'l
& Military
UnitMin. Max. Min. Max. Min. Max.
WRITE CYCLE
t
WC
Write Cycle Time 20
____
25
____
35
____
ns
t
EW
Chip Enable to End-of-Write 15
____
20
____
30
____
ns
t
AW
Address Valid to End-of-Write 15
____
20
____
30
____
ns
t
AS
Address Set-up Time 0
____
0
____
0
____
ns
t
WP
Write Pulse Width 15
____
20
____
25
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
ns
t
DW
Data Valid to End-of-Write 15
____
15
____
20
____
ns
t
HZ
Output High-Z Time
(1,2)
____
15
____
15
____
20 ns
t
DH
Data Hold Time
(3)
0
____
0
____
3
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____
15
____
15
____
20 ns
t
OW
Output Active from End-of-Write
(1,2,3)
3
____
3
____
3
____
ns
t
WDD
Write Pulse to Data Delay
(4)
____
40
____
50
____
60 ns
t
DDD
Write Data Valid to Read Data Delay
(4)
____
30
____
30
____
35 ns
2720 tbl 10a
Symbol Parameter
7134X45
Com'l &
Military
7134X55
Com'l, Ind
& Military
7134X70
Com'l &
Military
UnitMin. Max. Min. Max. Min. Max.
WRITE CYCLE
t
WC
Write Cycle Time 45
____
55
____
70
____
ns
t
EW
Chip Enable to End-of-Write 40
____
50
____
60
____
ns
t
AW
Address Valid to End-of-Write 40
____
50
____
60
____
ns
t
AS
Address Set-up Time 0
____
0
____
0
____
ns
t
WP
Write Pulse Width 40
____
50
____
60
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
ns
t
DW
Data Valid to End-of-Write 20
____
25
____
30
____
ns
t
HZ
Output High-Z Time
(1,2)
____
20
____
25
____
30 ns
t
DH
Data Hold Time
(3)
3
____
3
____
3
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____
20
____
25
____
30 ns
t
OW
Output Active from End-of-Write
(1,2,3)
3
____
3
____
3
____
ns
t
WDD
Write Pulse to Data Delay
(4)
____
70
____
80
____
90 ns
t
DDD
Write Data Valid to Read Data Delay
(4)
____
45
____
55
____
70 ns
2720 tbl 10b