19
LTC3737
3737fa
APPLICATIO S I FOR ATIO
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If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC3737 will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple current and ripple voltage will increase.
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting efficiency and which change would produce the
most improvement. Efficiency can be expressed as:
Efficiency = 100% - (L1 + L2 + L3 + …)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, five main sources usually account for most of the
losses in LTC3737 circuits: 1) LTC3737 DC bias current,
2) MOSFET gate charge current, 3) I
2
R losses, 4) voltage
drop of the output diode and 5) transition losses.
1) The V
IN
(pin) current is the DC supply current, given in
the electrical characteristics, that excludes MOSFET
driver currents. V
IN
current results in a small loss that
increases with V
IN
.
2) MOSFET gate charge current results from switching the
gate capacitance of the power MOSFET. Each time a
MOSFET gate is switched from low to high to low again,
a packet of charge dQ moves from PV
IN
to ground. The
resulting dQ/dt is a current out of PV
IN
, which is
typically much larger than the DC supply current. In
continuous mode, I
GATECHG
= f • Q
P
.
3) I
2
R losses are calculated from the DC resistances of the
MOSFET, inductor and sense resistor. In continuous
mode, the average output current flows through L but
is “chopped” between the P-channel MOSFET and the
output diode. The MOSFET R
DS(ON)
multiplied by duty
cycle can be summed with the resistance of L to obtain
I
2
R losses.
4) The output diode is a major source of power loss at high
currents and is worse at high input voltages. The diode
loss is calculated by multiplying the forward voltage
times the load current times the diode duty cycle.
5) Transition losses apply to the external MOSFET and
increase with higher operating frequencies and input
voltages. Transition losses can be estimated from:
Transition Loss = 2(V
IN
)
2
• I
O(MAX)
• C
RSS
(f)
Other losses, including C
IN
and C
OUT
ESR dissipative
losses and inductor core losses, generally account for less
than 2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to (I
LOAD
)(ESR), where ESR is the effective series
resistance of
COUT
. I
LOAD
also begins to charge or dis-
charge C
OUT
, which generates a feedback error signal. The
regulator loop then returns V
OUT
to its steady-state value.
During this recovery time, V
OUT
can be monitored for over-
shoot or ringing. OPTI-LOOP
®
compensation allows the
transient response to be optimized over a wide range of
output capacitance and ESR values.
The I
TH
series R
C
-C
C
filter (see Functional Diagram) sets
the dominant pole-zero loop compensation. The I
TH
exter-
nal components shown in the Figure 1 circuit will provide
an adequate starting point for most applications. The
values can be modified slightly (from 0.2 to 5 times their
suggested values) to optimize transient response once the
final PC layout is done and the particular output capacitor
type and value have been determined. The output capaci-
tors need to be decided upon because the various types
and values determine the loop feedback factor gain and
phase. An output current pulse of 20% to 100% of full load
current having a rise time of 1µs to 10µs will produce
output voltage and I
TH
pin waveforms that will give a sense
of the overall loop stability. The gain of the loop will be
increased by increasing R
C
, and the bandwidth of the loop
will be increased by decreasing C
C
. The output voltage
settling behavior is related to the stability of the closed-
loop system and will demonstrate the actual overall supply
performance. For a detailed explanation of optimizing the
compensation components, including a review of control
loop theory, refer to Application Note 76.
OPTI-LOOP is a registered trademark of Linear Technology Corporation.
20
LTC3737
3737fa
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25)(C
LOAD
).
Thus a 10µF capacitor would require a 250µs rise time,
limiting the charging current to about 200mA.
Design Example
As a design example, assume V
IN
will be operating from a
maximum of 4.2V down to a minimum of 2.7V (powered
by a single lithium-ion battery). Load current requirement
is a maximum of 2.5A, but most of the time it will be in a
standby mode requiring only 2mA. Efficiency at both low
and high load currents is important. Burst Mode operation
at light loads is desired. Output voltage is 2.5V. The IPRG
pin will be tied to V
IN
, so the maximum current sense
threshold V
SENSE(MAX)
is approximately 204mV.
Maximum Duty Cycle =
V
OUT
+
+
=
V
VV
D
IN MIN D()
%93
From Figure 2, SF = 57%.
RSF
V
I
DS ON MAX
SENSE MAX
OUT MAX T
()( )
()
()
•.•
.
=
=
5
6
09
0 027
ρ
A 0.025 Si3473DV P-channel MOSFET is close to this
value.
The PLLLPF pin will be left floating, so the LTC3737 will
operate at its default frequency of 550kHz. For continuous
Burst Mode operation, the required minimum inductor
value is:
L
VV
kHz
V
VV
VV
H
MIN
=
+
+
42 25
550
0 051
0 025
25 03
42 03
140
.–.
.
.
..
..
.
APPLICATIO S I FOR ATIO
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PC Board Layout Checklist
When laying out the printed circuit board, use the follow-
ing checklist to ensure proper operation of the LTC3737.
The power loop (input capacitor, MOSFET, inductor,
output diode, output capacitor) of each channel should
be as small as possible and isolated as much as
possible from the other channel’s power loop. It is
better to have two separate, smaller valued input
capacitors (e.g., two 10µF—one for each channel)
than it is to have a single larger valued capacitor (e.g.,
one 22µF) that the channels share with a common
connection.
The signal and power grounds should be kept separate.
The signal ground consists of the feedback resistor
dividers, I
TH
compensation networks and the SGND
pin.
The power grounds consist of the (–) terminal of the
input and output capacitors, the anode of the Schottky
diodes and the PGND pins. Each channel should have
its own power ground for its power loop as described
above. The power grounds for the two channels should
connect together at a common point. It is most impor-
tant to keep the ground paths with high switching
currents away from each other.
Put the feedback resistors close to the V
FB
pins. The I
TH
compensation components should also be very close to
the LTC3737.
The current sense traces (SENSE
+
and SENSE
/SW)
should be Kelvin connections right at the P-channel
MOSFET source and drain.
Keep the switch nodes (SW1, SW2) and the gate driver
nodes (PGATE1, PGATE2) away from the small-signal
components, especially the opposite channel’s feed-
back resistors, I
TH
compensation components and the
current sense pins (SENSE
+
and SENSE
/SW).
21
LTC3737
3737fa
V
FB2
7
24
220pF
100pF
15k
220pF
100pF
15k
1
187k
59k
1µF
118k
59k
59k
118k
22 21 20 19
M1
D1
C1
47µF
C3
10µF
×2
V
IN
5V
V
OUT1
2.5V
3A
C2
47µF
M2
L2
2.2µH
L1
2.2µH
8 6 10 11 12
PV
IN2
I
TH2
TRACK SW2 SENSE2
+
V
FB1
IPRG1
IPRG2
PLLLPF
SGND
V
IN
PGOOD
18
17
16
15
14
13
23
2
3
4
5
9
SYNC/MODE
PGATE1
PGND
PGATE2
RUN/SS
NC
NCI
TH1
SW1 SENSE1
+
LTC3737EUF
PV
IN1
D2
+
+
V
OUT2
1.8V
3A
3737 TA01
C1, C2: SANYO 6TPA47M
C3: TAIYO YUDEN LMK325BJ106K-T
D1, D2: IR 10BQ015
L1, L2: COILCRAFT D03316P-22
M1, M2: Si9803DY
1M
10
2-Phase, 750kHz, Burst Mode Dual Output Step-Down DC/DC Converter
TYPICAL APPLICATIO S
U
V
FB2
7
24
220pF
100pF
15k
220pF
100pF
15k
1
187k
59k
1µF
118k
59k
59k
118k
22 21 20 19
M1
D1
C1
150µF
C3
22µF
×2
V
IN
5V
V
OUT1
2.5V
5A
C2
150µF
M2
L2
1.5µH
L1
1.5µH
8 6 10 11 12
C
SS
10nF
PV
IN2
I
TH2
TRACK SW2 SENSE2
+
V
FB1
IPRG1
IPRG2
PLLLPF
SGND
V
IN
PGOOD
18
17
16
15
14
13
23
2
3
4
5
9
SYNC/MODE
PGATE1
PGND
PGATE2
RUN/SS
NC
NCI
TH1
SW1 SENSE1
+
LTC3737EUF
PV
IN1
D2
+
+
V
OUT2
1.8V
5A
3737 F13
C1, C2: SANYO 4TPB150MC
C3: TAIYO YUDEN LMK325BJ106K-T
D1, D2: SBM540
L1, L2: VISHAY IHLP-2525CZ-01-1.5
M1, M2: FDC602P
10
1M
APPLICATIO S I FOR ATIO
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Figure 13. 2-Phase, 550kHz, Dual Output Step-Down DC/DC Converter

LTC3737EGN#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 2-Phase Controller w/Tracking
Lifecycle:
New from this manufacturer.
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