LT3688
23
3688f
C
POR
= t
RST
• 200
pF
ms
⎛
⎝
⎜
⎞
⎠
⎟
This equation is accurate for reset timeout periods of 1ms,
or greater. To program faster timeout periods, see the
Reset Timeout Period vs Capacitance graph in the Typical
Characteristics section. Leaving the C
POR
pin unconnected
will generate a minimum reset timeout of approximately
65s. Maximum reset timeout is limited by the largest
available low leakage capacitor. The accuracy of the
timeout period will be affected by capacitor leakage (the
nominal charging current is 2.5A), capacitor tolerance
and temperature coeffi cient. A low leakage, low tempco,
capacitor is recommended.
Selecting the Watchdog Timing Capacitor
The watchdog timeout period is adjustable and can be
optimized for software execution. The watchdog window
upper boundary, t
WDU
is adjusted by connecting a capacitor,
C
WDT
, between the C
WDT
pin and ground. Given a specifi ed
watchdog timeout period, the capacitor is determined by:
C
WDT
= t
WDU
•50
pF
ms
⎛
⎝
⎜
⎞
⎠
⎟
The window lower boundary (t
WDL
) and the watchdog
timeout (t
WDTO
) have a fi xed relationship to t
WDU
for a
given capacitor. The window lower boundary is related to
t
WDU
by the following:
t
WDL
=
1
16
•t
WDU
The watchdog timeout is related to t
WDU
by the following:
t
WDTO
=
1
8
•t
WDU
Leaving the C
WDT
pin unconnected will generate a minimum
watchdog window upper boundary of approximately 200s.
Maximum window upper boundary is limited by the largest
available low leakage capacitor. The timing accuracy of the
reset and watchdog signals depends on the initial accuracy
and stability of the programing capacitors. Use capacitors
with specifi ed accuracy, leakage and voltage and temperature
coeffi cients. For surface mount ceramic capacitors C0G and
NP0 types are superior to alternatives such as X5R and X7R.
APPLICATIONS INFORMATION
5µs/DIV
V
SW
10V/DIV
I
L
500mA/DIV
3688 F12
Figure 12. The LT3688 Reduces Its Frequency to Below
70kHz to Protect Against Shorted Output with 36V Input
Shorted and Reversed Input Protection
If an inductor is chosen to prevent excessive saturation, the
LT3688 will tolerate a shorted output. When operating in
short-circuit condition, the LT3688 will reduce its frequency
until the valley current is at a typical value of 1.2A (see Figure
12). There is another situation to consider in systems where
the output will be held high when the input to the LT3688 is
absent. This may occur in battery charging applications or
in battery backup systems where a battery or some other
supply is diode ORed with the LT3688’s output. If the V
IN
pin is allowed to fl oat and the EN/UVLO pin is held high
(either by a logic signal or because it is tied to V
IN
), then
the LT3688’s internal circuitry will pull its quiescent current
through its SW pin. This is fi ne if the system can tolerate a
few mA in this state. If the EN/UVLO pin is grounded, the
SW pin current will drop to essentially zero.
However, if the V
IN
pin is grounded while the output is
held high, then parasitic diodes inside the LT3688 can
pull large currents from the output through the SW pin
and the V
IN
pin. Figure 13 shows a circuit that will run
only when the input voltage is present and that protects
against a shorted or reversed input.
PCB Layout
For proper operation and minimum EMI, care must be taken
during printed circuit board layout. Figure 14 shows the
recommended component placement with trace, ground
plane and via locations. Note that large, switched currents
fl ow in the LT3688’s V
IN
, DA and SW pins, the catch diode
(D1) and the input capacitor (C1). The loop formed by
