ISL6530CRZ Datasheet ISL6530CBZ, ISL6530CRZ, ISL6530CB | P7-P9

FN9052.2

November 15, 2004

While the V

supply “floats”, it is held to about 50% of

DDQ

via a low current window regulator which drives V

via the SENSE2 pin. The window regulator can overcome up

to at least 10mA of leakage on V

While V2_SD is high, PGOOD is low.

PHASE1 and PHASE2

Connect PHASE1 and PHASE2 to the corresponding upper

MOSFET source. This pin is used as part of the upper

MOSFET bootstrapped drives. PHASE1 is used to monitor

the voltage drop across the upper MOSFET of the V

DDQ

regulator for over-current protection. The PHASE1 pin is

monitored by the adaptive shoot through protection circuitry

to determine when the upper FET of the V

DDQ

supply has

turned off.

FB1, COMP1, FB2, and COMP2

COMP1, COMP2, FB1, and FB2 are the available external

pins of the error amplifiers. The FB1 and FB2 pins are the

inverting inputs of each error amplifier and the COMP1 and

COMP2 pins are the associated outputs. An appropriate AC

network across these pins is used to compensate the

voltage-controlled feedback loop of each converter.

VREF and VREF_IN

VREF produces a voltage equal to one half of the voltage on

SENSE1. This low current output is connected to the VREF

input of the DDRAM devices being powered. This same

voltage is used as the reference input of the V

error

amplifier. Thus V

is controlled to 50% of V

DDQ

VREF_IN is used as an option to overdrive the internal

resistor divider network that sets the voltage for both

VREF_OUT and the reference voltage for the V

supply. A

100pF capacitor between VREF_IN and ground is

recommended for proper operation.

PVCC1

This is the positive supply for the lower gate driver, LGATE1.

PVCC1 is connected to a well decoupled 5V.

SENSE1 and SENSE2

Both SENSE1 and SENSE2 are connected directly to the

regulated outputs of the V

DDQ

and V

supplies,

respectively. SENSE1 is used as an input to create the

voltage at VREF_OUT and the reference voltage for the V

supply. SENSE2 is used as the regulation point for the

window regulator that is enabled in V2_SD mode.

Functional Description

Overview

The ISL6530 contains control and drive circuitry for two

synchronous buck PWM voltage regulators. Both regulators

utilize 5V bootstrapped output topology to allow use of low

cost N-channel MOSFETs. The regulators are driven by

300kHz clocks. The clocks are phase locked and displaced

to minimize noise coupling between the controllers.

The first regulator includes a precision 0.8V reference and is

intended to provide the proper V

DDQ

to a DDRAM memory

system. The V

DDQ

controller implements overcurrent

protection utilizing the r

DS(ON)

of the upper MOSFET.

Following a fault condition, the V

DDQ

regulator is softstarted

via a digital softstart circuit.

Included in the ISL6530 is a precision V

REF

reference

output. V

REF

is a buffered representation of .5xV

DDQ

. V

REF

is derived via a precision internal resistor divider connected

to the SENSE1 terminal.

The second PWM regulator is designed to provide V

termination for the DDRAM signal lines. The reference to the

regulator is V

REF

. Thus the V

regulator provides a

termination voltage equal to .5xV

DDQ

. The drain of the upper

MOSFET of the V

supply is connected to the regulated

DDQ

voltage. The V

controller is designed to enable both

sinking and sourcing current on the V

rail.

Two benefits result from the ISL6530 dual controller

topology. First, as VREF is always .5xV

DDQ

, the V

supply

will track the V

DDQ

supply during softstart cycles. Second,

the overcurrent protection incorporated into the V

DDQ

supply will simultaneously protect the V

supply.

Initialization

The ISL6530 automatically initializes upon application of

input power. Special sequencing of the input supplies is not

necessary. The Power-On Reset (POR) function continually

monitors the input bias supply voltage at the VCC pin. The

POR function initiates soft-start operation after the 5V bias

supply voltage exceeds its POR threshold.

Soft-Start

The POR function initiates the digital soft start sequence. The

PWM error amplifier reference input for the VDDQ regulator is

clamped to a level proportional to the soft-start voltage. As the

soft-start voltage slews up, the PWM comparator generates

PHASE pulses of increasing width that charge the output

capacitor(s). This method provides a rapid and controlled

output voltage rise. The soft start sequence typically takes

about 7ms.

With the V

regulator reference held at it will

automatically track the ramp of the V

DDQ

softstart, thus

enabling a soft-start for V

Figure 2 shows the soft-start sequence for a typical application.

At t0, the +5V VCC bias voltage starts to ramp. Once the

voltage on VCC crosses the POR threshold at time t1, both

outputs begin their soft-start sequence. The triangle waveforms

from the PWM oscillators are compared to the rising error

amplifier output voltage. As the error amplifier voltage

increases, the pulse-widths on the UGATE pins increase to

reach their steady-state duty cycle at time t2.

--- V

DDQ



ISL6530

FN9052.2

November 15, 2004

Shoot-Through Protection

A shoot-through condition occurs when both the upper

MOSFET and lower MOSFET are turned on simultaneously,

effectively shorting the input voltage to ground. To protect

the regulators from a shoot-through condition, the ISL6530

incorporates specialized circuitry which insures that

complementary MOSFETs are not ON simultaneously.

The adaptive shoot-through protection utilized by the V

DDQ

regulator looks at the lower gate drive pin, LGATE1, and the

phase node, PHASE1, to determine whether a MOSFET is

ON or OFF. If PHASE1 is below 0.8V, the upper gate is

defined as being OFF. Similarly, if LGATE1 is below 0.8V, the

lower MOSFET is defined as being OFF. This method of

shoot-through protection allows the V

DDQ

regulator to

source current only.

Due to the necessity of sinking current, the V

regulator

employs a modified protection scheme from that of the

DDQ

regulator. If the voltage from UGATE2 or from

LGATE2 to GND is less than 0.8V, then the respective

MOSFET is defined as being OFF and the other MOSFET is

turned ON.

Since the voltage of the lower MOSFET gates and the upper

MOSFET gate of the V

supply are being measured to

determine the state of the MOSFET, the designer is

encouraged to consider the repercussions of introducing

external components between the gate drivers and their

respective MOSFET gates before actually implementing

such measures. Doing so may interfere with the shoot-

through protection.

Power Down Mode

DDRAM systems include a sleep state in which the V

DDQ

voltage to the memories is maintained, but signaling is

suspended. During this mode the V

termination voltage is

no longer needed. The only load placed on the V

bus is

the leakage of the associated signal pins of the DDRAM and

memory controller ICs.

When the V2_SD input of the ISL6530 is driven high, the

regulator is placed into a “sleep” state. In the sleep

state the main V

regulator is disabled, with both the

upper and lower MOSFETs being turned off. The V

bus is

maintained at close to .5xVdd via a low current window

regulator which drives V

via the SENSE2 pin.

Maintaining V

at .5xV

DDQ

consumes negligible power

and enables rapid wake-up from sleep mode without the

need of softstarting the V

regulator. During this power

down mode, PGOOD is held LOW.

Output Voltage Selection

The output voltage of the V

DDQ

regulator can be

programmed to any level between V

(i.e. +5V) and the

internal reference, 0.8V. An external resistor divider is used

to scale the output voltage relative to the reference voltage

and feed it back to the inverting input of the error amplifier,

see Figure 3. However, since the value of R1 affects the

values of the rest of the compensation components, it is

advisable to keep its value less than 5k. R4 can be

calculated based on the following equation:

If the output voltage desired is 0.8V, simply route VOUT1

back to the FB pin through R1, but do not populate R4.

Reference Overdrive

The ISL6530 allows the designer to bypass the internal 50%

tracking of V

DDQ

that is used as the reference for V

. The

ISL6530 was designed to divide down the V

DDQ

voltage by

50% through two internal matched resistances. These

resistances are typically 200k.

FIGURE 2. SOFT-START INTERVAL

TIME

VCC (5V)

(1V/DIV)

DDQ

(2.5V)

(1.25V)

R1 0.8V

OUT1

0.8V–

--------------------------------------=

FIGURE 3. OUTPUT VOLTAGE SELECTION OF V

DDQ

OUT1

+5V

DDQ

OUT

ISL6530

FB1

UGATE1

VCC

BOOT1

COMP1

PHASE1

LGATE1

ISL6530

FN9052.2

November 15, 2004

One method that may be employed to bypass the internal

reference generation is to supply an external reference

directly to the V

REF_IN

pin. When doing this the SENSE1 pin

must remain unconnected. Caution must be exercised when

using this method as the V

regulator does not employ a

soft-start of its own.

A second method would be to overdrive the internal

resistors. Figure 4 shows how to implement this method. The

external resistors used to overdrive the internal resistors

should be less than 2k and have a tolerance of 1% or

better. This method still supplies a buffer between the

resistor network and any loading on the V

REF

pin. If there is

no loading on the V

REF

pin, then no buffering is necessary

and the reference voltage created by the resistor network

can be tied directly to V

REF

Converter Shutdown

Pulling and holding the OCSET/SD pin below 0.8V will

shutdown both regulators. During this state, PGOOD will be

held LOW. Upon release of the OCSET/SD pin, the IC enters

into a soft start cycle which brings both outputs back into

regulation.

Voltage Monitoring

The ISL6530 offers a PGOOD signal that will communicate

whether the regulation of both V

DDQ

and V

are within

±15% of regulation, the V2_SD pin is held low and the bias

voltage of the IC is above the POR level. If all the criteria

above are true, the PGOOD pin will be at a high impedence

level. When one or more of the criteria listed above are false,

the PGOOD pin will be held low.

Overcurrent Protection

The overcurrent function protects the converter from a shorted

output by using the upper MOSFET on-resistance, r

DS(ON)

, of

DDQ

to monitor the current. This method enhances the

converter’s efficiency and reduces cost by eliminating a

current sensing resistor.

The over-current function cycles the soft-start function in a

hiccup mode to provide fault protection. A resistor (R

OCSET

)

programs the overcurrent trip level (see Figure 1). An internal

40A (typical) current sink develops a voltage across R

OCSET

that is referenced to V

. When the voltage across the upper

MOSFET of V

DDQ

(also referenced to V

) exceeds the

voltage across R

OCSET

, the overcurrent function initiates a

soft-start sequence.

Figure 5 illustrates the protection feature responding to an

over current event on V

DDQ

. At time T0, an over current

condition is sensed across the upper MOSFET of the V

DDQ

regulator. As a result, both regulators are quickly shutdown

and the internal soft-start function begins producing soft-start

ramps. The delay interval seen by the output is equivalent to

three soft-start cycles. The fourth internal soft-start cycle

initiates a normal soft-start ramp of the output, at time T1.

Both outputs are brought back into regulation by time t2, as

long as the overcurrent event has cleared.

Had the cause of the overcurrent still been present after the

delay interval, the overcurrent condition would be sensed

and both regulators would be shut down again for another

delay interval of three soft-start cycles. The resulting hiccup

mode style of protection would continue to repeat

indefinitely.

The overcurrent function will trip at a peak inductor current

PEAK)

determined by:

where I

OCSET

is the internal OCSET current source (40A

typical). The OC trip point varies mainly due to the MOSFET

FIGURE 4. V

REFERENCE OVERDRIVE

VREF

VREF_IN

SENSE1

TO ERROR

AMPLIFIER

ISL6530

DDQ

FIGURE 5. OVERCURRENT PROTECTION RESPONSE

TIME

DDQ

(2.5V)

T0 T2

(1.25V)

INTERNAL SOFT-START FUNCTION

DELAY INTERVAL

PEAK

OCSET

x R

OCSET

DS ON

-----------------------------------------------------=

ISL6530

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

ISL6530CRZ

Mfr. #:

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Manufacturer:

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ISL6530CRZ

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