1999 Oct 01 2
Philips Semiconductors Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
74HCT7273
FEATURES
• ESD protection:
HBM EIA/JESD22-A114-A
Exceeds 2000 V
MM EIA/JESD22-A115-A
Exceeds 200 V
• Ideal buffer for MOS
microprocessor or memory
• Eight positive edge-triggered
D-type flip-flops
• Common clock and master reset
• Output capability: standard (open
drain)
• I
CC
category: MSI.
DESCRIPTION
The 74HCT7273 is a high-speed SI-gate CMOS device and is pin compatible
with Low power Schottky TTL (LSTTL). It is specified in compliance with
JEDEC standard no 7A.
The 74HCT7273 has eight edge-triggered D-type flip-flops with individual D
inputs and Q outputs. The common Clock (CP) and Master Reset (MR) inputs
load and reset (clear) all flip-flops simultaneously.
The state of each D input, one set-up time before the LOW-to-HIGH clock
transition, is transferred to the corresponding output (Q
n
) of the flip-flop.
A LOW level on the MR input forces all outputs LOW, independently of the clock
or data inputs.
The device is useful for applications requiring true outputs only and clock and
master reset inputs that are common to all storage elements.
The 74HCT7273 has open-drain N-outputs, which are clamped by a diode
connected to V
CC
. When a HIGH is clocked in the flip-flop, the output comes in
the high-impedance OFF-state. The output may now be pulled to any voltage
between GND and V
Omax
. This allows the device to be used as a LOW-to-HIGH
or HIGH-to-LOW level shifter. For digital operation and OR-tied output
applications, the device must have a pull-up resistor to establish a logic HIGH
level.
QUICK REFERENCE DATA
Ground = 0 V; T
amb
=25°C; t
r
=t
f
= 6.0 ns.
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in µW).
P
D
=C
PD
× V
CC
2
× f
i
+ ∑ (C
L
× V
CC
2
× f
o
)+∑(V
0
2
/R
L
) × duty factor LOW where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
∑ (C
L
× V
CC
2
× f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
R
L
= pull-up resistor in MΩ;
V
CC
= supply voltage in Volts.
2. The condition is V
I
= GND to V
CC
− 1.5 V.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
t
PZL
/t
PLZ
propagation delay C
L
= 50 pF; V
CC
= 4.5 V
CP to Q
n
16 ns
MR to Q
n
23 ns
f
max
maximum clock frequency 56 MHz
C
I
input capacitance 3.5 pF
C
PD
power dissipation capacitance C
L
= 50 pF; f = 1 MHz; notes 1 and 2 37 pF
