Data Sheet ADP3303
THEORY OF OPERATION
The new anyCAP LDO ADP3303 uses a single control loop for
regulation and reference functions. The output voltage is sensed
by a resistive voltage divider consisting of R1 and R2, which is
varied to provide the available output voltage options. Feedback
is taken from this network by way of a series diode (D1) and a
second resistor divider (R3 and R4) to the input of an amplifier.
Figure 22. Functional Block Diagram
A very high gain error amplifier is used to control this loop. The
amplifier is constructed so that at equilibrium it produces a large,
temperature proportional input offset voltage that is repeatable
and very well controlled. The temperature-proportional offset
voltage is combined with the complementary diode voltage to
form a virtual band gap voltage, implicit in the network,
although it never appears explicitly in the circuit. Ultimately,
this patented design makes it possible to control the loop with
only one amplifier. This technique also improves the noise
characteristics of the amplifier by providing more flexibility on
the tradeoff of noise sources that leads to a low noise design.
The R1, R2 divider is chosen in the same ratio as the band gap
voltage to the output voltage. Although the R1, R2 resistor divider
is loaded by the diode D1 and a second divider consisting of R3
and R4, the values are chosen to produce a temperature stable
output. This unique arrangement specifically corrects for the
loading of the divider to avoid the error resulting from base
current loading in conventional circuits.
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this special
noninverting driver enables the frequency compensation to
include the load capacitor in a pole splitting arrangement to
achieve reduced sensitivity to the value, type, and ESR of the
load capacitance.
Most LDOs place strict requirements on the range of ESR values
for the output capacitor because they are difficult to stabilize due
to the uncertainty of load capacitance and resistance. Moreover,
the ESR value, required to keep conventional LDOs stable, changes
depending on load and temperature. These ESR limitations make
designing with LDOs more difficult because of their unclear
specifications and extreme variations over temperature.
This is not true with the ADP3303 anyCAP LDO. The ADP3303
can be used with virtually any capacitor, with no constraint on
the minimum ESR. The innovative design allows the circuit to
be stable with just a small 0.47 µF capacitor on the output.
Additional advantages of the pole splitting scheme include
superior line noise rejection and very high regulator gain, which
leads to excellent line and load regulation. An impressive ±1.4%
accuracy is guaranteed over line, load, and temperature.
Additional features of the circuit include current limit, thermal
shutdown, and noise reduction. Compared to standard solutions
that give warning after the output loses regulation, the ADP3303
provides improved system performance by enabling the
ERR
pin to give warning before the device loses regulation.
As the temperature of the chip rises above 165°C, the circuit
activates a soft thermal shutdown, indicated by a signal low on
the
ERR
pin, to reduce the current to a safe level.
To reduce the noise gain of the loop, the node of the main divider
network (a) is made available at the noise reduction (NR) pin,
which can be bypassed with a small capacitor (10 nF to 100 nF).
g
m
PTAT
V
OS
R4
R3
D1
R1
ATTENUATION
(V
BANDGAP
/V
OUT
)
R2
(a)
COMPENSATION
CAPACITOR
NONINVERTING
WIDEBAND
DRIVER
Q1
IN
C
LOAD
OUT
ADP3303
R
LOAD
PTAT
CURRENT
GND
10335-022
Rev. C | Page 9 of 16
ADP3303 Data Sheet
APPLICATION INFORMATION
CAPACITOR SELECTION
Output Capacitors
As with any micropower device, output transient response is a
function of the output capacitance. The ADP3303 is stable with
a wide range of capacitor values, types and ESR. A capacitor as
low as 0.47 µF is all that is needed for stability; larger capacitors
can be used if high output current surges are anticipated. The
ADP3303 is stable with extremely low ESR capacitors (ESR ≈ 0),
such as multilayer ceramic capacitors (MLCC) or OSCON.
Input Bypass Capacitor
An input bypass capacitor is not required. For applications in
which the input source is high impedance or far from the input
pins, use a bypass capacitor. Connecting a 0.47 µF capacitor
from the input pins to ground reduces the sensitivity of the
circuit to PCB layout. If a larger value output capacitor is used,
then a larger value input capacitor is also recommended.
NOISE REDUCTION
A noise reduction capacitor (C
NR
) can be used to further reduce
the noise by 6 dB to 10 dB (see Figure 23). Low leakage capacitors
in the 10 nF to 100 nF range provide the best performance.
Since the noise reduction pin (NR) is internally connected to a
high impedance node, any connection to this node must be
carefully done to avoid noise pickup from external sources. The
pad connected to this pin must be as small as possible. Long
PCB traces are not recommended.
Figure 23. Noise Reduction Circuit
THERMAL OVERLOAD PROTECTION
The ADP3303 is protected against damage due to excessive power
dissipation by its thermal overload protection circuit, which
limits the die temperature to a maximum of 165°C. Under
extreme conditions (that is, high ambient temperature and
power dissipation), where die temperature starts to rise above
165°C, the output current is reduced until the die temperature
drops to a safe level. The output current is restored when the
die temperature is reduced.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, device power dissipation must be externally limited
so that junction temperatures does not exceed 125°C.
CALCULATING JUNCTION TEMPERATURE
Device power dissipation is calculated as follows:
P
D
= (V
IN
– V
OUT
) I
LOAD
+ (V
IN
) I
GND
where:
I
LOAD
and I
GND
are load current and ground current.
V
IN
and V
OUT
are input and output voltages, respectively.
Assuming I
LOAD
= 200 mA, I
GND
= 2 mA, V
IN
= 7 V and V
OUT
=
5.0 V, device power dissipation is:
P
D
= (7 V 5 V) 200 mA + (7 V) 2 mA = 414 mW
The proprietary package used in the ADP3303 has a thermal
resistance of 96°C/W, significantly lower than a standard 8-lead
SOIC_N package at 170°C/W.
Junction temperature above ambient temperature is
approximately equal to:
0.414 W × 96°C/W = 39.7°C
To limit the maximum junction temperature to 125°C,
maximum ambient temperature must be lower than:
T
AMAX
= 125°C 40°C = 85°C
PRINTED CIRCUIT BOARD LAYOUT
CONSIDERATION
All surface mount packages rely on the traces of the PCB to
conduct heat away from the package.
In standard packages, the dominant component of the heat
resistance path is the plastic between the die attach pad and the
individual leads. In typical thermally enhanced packages, one or
more of the leads are fused to the die attach pad, significantly
decreasing this component. To make the improvement meaningful,
however, a significant copper area on the PCB must be attached
to these fused pins.
The patented thermal coastline lead frame design of the ADP3303
(see Figure 24) uniformly minimizes the value of the dominant
portion of the thermal resistance. It ensures that heat is conducted
away by all pins of the package. This yields a very low, 96°C/W,
thermal resistance for an SOIC_N package, without any special
board layout requirements, relying on the normal traces connected
to the leads. The thermal resistance can be decreased approximately
an additional 10% by attaching a few square cm of copper area
to the IN pin of the ADP3303.
Do not use solder mask or silkscreen on the PCB traces
adjacent to the pins of the ADP3303 since it increases the
junction to ambient thermal resistance of the package.
IN
OUT
ERR
GND
ADP3303-5.0
NR
+
6
7
8
1
2
3
4
5
ON
OFF
+
SD
C
NR
10nF
C2
10µF
R1
330
E
OUT
C1
1µF
V
OUT
= 5V
V
IN
SD
10335-023
Rev. C | Page 10 of 16
Data Sheet ADP3303
Figure 24. Thermal Coastline
ERROR FLAG DROPOUT DETECTOR
The ADP3303 maintains its output voltage over a wide range of
load, input voltage and temperature conditions. If, for example,
the output is about to lose regulation by reducing the supply
voltage below the combined regulated output and drop-out
voltages, the
ERR
flag is activated. The
ERR
output is an open
collector, which is driven low.
Once set, the hysteresis of the
ERR
flag keeps the output low
until a small margin of operating range is restored either by
raising the supply voltage or reducing the load.
SHUTDOWN MODE
Applying a TTL high signal to the shutdown (
SD
) pin, or tying
it to the input pin, turns the output on. Pulling
SD
down to 0.3 V
or below, or tying it to ground, turns the output off. In shutdown
mode, quiescent current is reduced to much less than 1 µA.
COPPER PADDLE
1
2
3
4
8
7
6
5
COPPER
LEAD-FRAME
10335-024
Rev. C | Page 11 of 16

ADP3303ARZ-5-REEL

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Linear Voltage Regulators High Acc 200mA LDO
Lifecycle:
New from this manufacturer.
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