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AT17F080-30BJC
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
13
AT17F0
40/080
3039G–CNF
G–4/2
004
Orde
ri
ng
I
n
form
a
tio
n
Memory Size
Ord
ering Code
P
ackage
Operati
on Range
4-Mbi
t
A
T17F040-3
0CC
A
T17F0
40-30JC
A
T17F0
40-30VJC
8C
N
4 - 8 L
A
P
20J - 20 PLCC
20J - 20 PLCC
Commercial
(0
°
C to 70
°
C)
A
T17F040-3
0CI
A
T17F0
40-30JI
A
T17F0
40-30VJI
8C
N
4 - 8 L
A
P
20J - 20 PLCC
20J - 20 PLCC
Indus
trial
(-4
0
°
C to 85
°
C)
8-Mbi
t
A
T17F080-3
0CC
A
T17F0
80-30JC
A
T17F0
80-30TQC
A
T17F0
80-30BJC
8C
N
4 - 8 L
A
P
20J - 20 PLCC
44A - 44 TQFP
44J - 44 PLCC
Commercial
(0
°
C to 70
°
C)
A
T17F080-3
0CI
A
T17F0
80-30JI
A
T17F0
80-30TQI
A
T17F0
80-30BJI
8C
N
4 - 8 L
A
P
20J - 20 PLCC
44A - 44 TQFP
44J - 44 PLCC
Indus
trial
(-4
0
°
C to 85
°
C)
Pack
ag
e
T
y
p
e
8CN4
8-l
ead, 6 m
m x 6 mm
x 1 mm
,
Leadless Ar
ra
y Pa
ckage (
LAP) – Pi
n-compa
tib
le wit
h 8-lead SOIC
/VO
ID
Pack
ages
20J
20-l
ead, P
lasti
c J-leaded Chip Carrier
(PLCC)
44A
44-lead,
T
hin (1.
0 mm) Plastic
Quad Flat
P
ac
kage Carrier
(TQFP)
44J
44-l
ead, P
lasti
c J-leaded Chip Carrier
(PLCC)
14
AT17F
040/080
3039G–CNF
G–4/200
4
P
ackagi
ng In
forma
tio
n
8CN4 – LAP
2325 Orchard P
arkway
San Jose, CA 95131
TITLE
DRA
WING NO
.
R
REV
.
8CN4
, 8-lead (6 x 6 x 1.04 mm Body), Lead Pitch 1.27 mm,
Leadless Array Package (LAP)
A
8CN4
11/14/01
Pin1 Corner
Marked Pin1 Indentifier
0.10 mm
TYP
4
3
2
1
5
6
7
8
Top View
L
b
e
L1
e1
Side View
A1
A
Bottom View
E
D
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
NOTE
A
0.94
1.04
1.14
A1
0.30
0.34
0.38
b
0.45
0.50
0.55
1
D
5.89
5.99
6.09
E
4.89
5.99
6.09
e
1.27 BSC
e1
1.10 REF
L
0.95
1.00
1.05
1
L1
1.25
1.30
1.35
1
Note:
1. Metal Pad Dimensions.
15
AT17F0
40/080
3039G–CNF
G–4/2
004
20
J – PLC
C
2325 Orchard P
arkway
San Jose, CA 95131
R
TITLE
DRA
WING NO
.
REV
.
Notes:
1.
This package conforms to JEDEC reference MS-018, Variation AA.
2.
Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
A
4.191
–
4.572
A1
2.286
–
3.048
A2
0.508
–
–
D
9.779
–
10.033
D1
8.890
–
9.042
Note 2
E
9.779
–
10.033
E1
8.890
–
9.042
Note 2
D2/E2
7.366
–
8.382
B
0.660
–
0.813
B1
0.330
–
0.533
e
1.270 TYP
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
NOTE
1.14(0.045) X 45˚
PIN NO
.
1
IDENTIFIER
1.14(0.045) X 45˚
0.51(0.020)MAX
0.318(0.0125)
0.191(0.0075)
A2
45˚ MAX (3X)
A
A1
B1
D2/E2
B
e
E1
E
D1
D
20J
, 20-lead, Plastic J-leaded Chip Carrier (PLCC)
B
20J
10/04/01
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
AT17F080-30BJC
Mfr. #:
Buy AT17F080-30BJC
Manufacturer:
Microchip Technology / Atmel
Description:
FPGA - Configuration Memory Serial Flash
Lifecycle:
New from this manufacturer.
Delivery:
DHL
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TNT
EMS
Payment:
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