LTM8058
8
8058fa
For more information www.linear.com/LTM8058
PIN FUNCTIONS
V
OUT1
(Bank 1): V
OUT1
and V
OUT
–
comprise the isolated
output of the LTM8058 flyback stage. Apply an external
capacitor between V
OUT1
and V
OUT
–
. Do not allow V
OUT
–
to exceed V
OUT1
.
V
OUT
–
(Bank 2): V
OUT
–
is the return for both V
OUT1
and
V
OUT2
. V
OUT1
and V
OUT
–
comprise the isolated output of
the LTM8058. In most applications, the bulk of the heat
flow out of the LTM8058 is through the GND and V
OUT
–
pads, so the printed circuit design has a large impact on
the thermal performance of the part. See the PCB Layout
and Thermal Considerations sections for more details.
Apply an external capacitor between V
OUT1
and V
OUT
–
.
V
OUT2
(Bank 3): The output of the secondary side linear
post regulator. Apply the load and output capacitor between
V
OUT2
and V
OUT
–
. See the Applications Information section
for more information on output capacitance and reverse
output characteristics.
GND (Bank 4): This is the local ground of the LTM8058
primary. In most applications, the bulk of the heat flow
out of the LTM8058 is through the GND and V
OUT
–
pads,
so the printed circuit design has a large impact on the
thermal
performance of the part. See the PCB Layout and
Thermal Considerations sections for more details.
V
IN
(Bank 5): V
IN
supplies current to the LTM8058’s
internal regulator and to the integrated power switch.
These pins must be locally bypassed with an external,
low ESR capacitor.
ADJ2 (pin A2): This is the input to the error amplifier of the
secondary side LDO post regulator. This pin is internally
clamped to ±7V. The ADJ2 pin voltage is 1.22V referenced
to V
OUT
–
and the output voltage range is 1.22V to 12V.
Apply a resistor from this pin to V
OUT
–
, using the equation
R
ADJ2
= 608.78/(V
OUT2
– 1.22)kΩ. If the post regulator is
not used, leave this pin floating.
BYP (Pin B2): The BYP pin is used to bypass the reference
of the LDO to achieve low noise performance from the
linear post regulator. The BYP pin is clamped internally
to ±0.6V relative to V
OUT
–
. A small capacitor from V
OUT2
to this pin will bypass the reference to lower the output
voltage noise. A maximum value of 0.01µF can be used
for reducing output voltage noise to a typical
20µV
RMS
over a 100Hz to 100kHz bandwidth. If not used, this pin
must be left unconnected.
RUN (Pin F3): A resistive divider connected to V
IN
and this
pin programs the minimum voltage at which the LTM8058
will operate. Below 1.24V, the LTM8058 does not deliver
power to the secondary. Above 1.24V, power will be de
-
livered to the secondary and 10µA will be fed into the SS
pin.
When RUN is less than 1.24V, the pin draws 2.5µA,
allowing for a programmable hysteresis. Do not allow a
negative voltage (relative to GND) on this pin.
ADJ1 (Pins G7): Apply a resistor from this pin to GND to
set the output voltage V
OUT1
relative to V
OUT
–
, using the
recommended value given in Table 1. If Table 1 does not
list the desired V
OUT1
value, the equation
R
ADJ1
= 28.4 V
OUT1
–0.879
kΩ
may be used to approximate the value. To the seasoned
designer, this exponential equation may seem unusual. The
equation is exponential due to nonlinear current sources
that are used to temperature compensate the regulation.
BIAS (Pin H5): This pin supplies the power necessary to
operate the LTM8058. It must be locally bypassed with a
low ESR capacitor of at least 4.7μF. Do not allow this pin
voltage to rise above V
IN
.
SS (Pin H6): Place a soft-start capacitor here to limit inrush
current and the output voltage ramp rate. Do not allow a
negative voltage (relative to GND) on this pin.
