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Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2009, Zarlink Semiconductor Inc. All Rights Reserved.
Features
• Can be used in systems to support the
requirements of ITU-T G.8262 for synchronous
Ethernet Equipment slave Clocks (EEC option 1
and 2)
• Meets jitter generation requirements of Telcordia
GR-253-CORE for OC-192, OC-48, OC-12 and
OC-3 rates
• Meets jitter generation requirements of ITU-T G.813
for STM-64, STM-16, STM-4 and STM-1 rates
• Synchronizes to standard telecom or Ethernet clock
and provides jitter filtered output clock for
SONET/SDH and Synchronous Ethernet line cards
• Synchronizes to telecom reference clocks (2 kHz,
N*8 kHz up to 77.76 MHz, 155.52 MHz) or to
Ethernet reference clocks (25 MHz, 50 MHz,
62.5 MHz, 125 MHz)
• Generates standard SONET/SDH clock rates (e.g.,
19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz,
622.08 MHz) or Ethernet clock rates (e.g., 25 MHz,
50 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for
synchronizing Ethernet PHYs
• Selectable loop bandwidth of 14 Hz, 28 Hz, or
890 Hz
• Configurable through a serial interface (SPI or I
2
C)
• DPLL can be configured to provide synchronous or
asynchronous clock outputs
• Supports IEEE 1149.1 JTAG Boundary Scan
Applications
• ITU-T G.8262 Line Cards which support 1 GbE
and 10 GbE interfaces
• SONET line cards up to OC-192
• SDH line cards up to STM-64
July 2009
Figure 1 - Simplified Functional Block Diagram
apll_clk
ref
diff
SONET/SDH/
Ethernet
APLL
DPLL
ref
/N
I
2
C/SPI JTAG
oscoosci
lock
hold
ZL30145
SyncE (10 GbE) SONET/SDH Rate
Conversion and Jitter Attenuator PLL
Short Form Data Sheet
Ordering Information
ZL30145GGG 64 Pin CABGA Trays
ZL30145GGG2 64 Pin CABGA* Trays
*Pb Free Tin/Silver/Copper
-40
o
C to +85
o
C
