6
AT49BV/LV160(T)/161(T)
1427L–FLASH–02/03
Any commands written to the chip during the embedded programming cycle will be ignored. If
a hardware reset happens during programming, the data at the location being programmed
will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase
operations can convert “0”s to “1”s. Programming is completed after the specified t
BP
cycle
time. The Data
Polling feature or the Toggle Bit feature may be used to indicate the end of a
program cycle. If the erase/program status bit is a “1”, the device was not able to verify that the
erase or program operation was performed successfully.
VPP PIN: The circuitry of the AT49BV/LV16X(T) is designed so that the device can be pro-
grammed or erased from the V
CC
power supply or from the VPP input pin. When V
PP
is greater
than 1.65V and less than or equal to the VCC pin, the device selects the V
CC
supply for pro-
gramming and erase operations. When the VPP pin is greater than the V
CC
supply, the device
will select the V
PP
input as the power supply for programming and erase operations. The
device will allow for some variations between the V
PP
input and the V
CC
power supply in its
selection of V
CC
or V
PP
for program or erase operations. If the VPP pin is within 0.3V of V
CC
for
2.65V < V
CC
< 3.6V, then the program or erase operations will use V
CC
and disregard the V
PP
input signal. When the V
PP
signal is used for program and erase operations, the V
PP
must be
in the 5V ± 0.5V or 12V ± 0.5V range to ensure proper operation. The V
pp
pin cannot be left
floating.
PROGRAM/ERASE STATUS: The device provides several bits to determine the status of a
program or erase operation: I/O2, I/O3, I/O5, I/O6 and I/O7. The “Status Bit Table” on page 12
and the following four sections describe the function of these bits. To provide greater flexibility
for system designers, the AT49BV/LV16X(T) contains a programmable configuration register.
The configuration register allows the user to specify the status bit operation. The configuration
register can be set to one of two different values, “00” or “01”. If the configuration register is set
to “00”, the part will automatically return to the read mode after a successful program or erase
operation. If the configuration register is set to a “01”, a Product ID Exit command must be
given after a successful program or erase operation before the part will return to the read
mode. It is important to note that whether the configuration register is set to a “00” or to a “01”,
any unsuccessful program or erase operation requires using the Product ID Exit command to
return the device to read mode. The default value (after power-up) for the configuration regis-
ter is “00”. Using the four-bus cycle Set Configuration Register command as shown in the
“Command Definition in Hex” table on page 13, the value of the configuration register can be
changed. Voltages applied to the RESET
pin will not alter the value of the configuration regis-
ter. The value of the configuration register will affect the operation of the I/O7 status bit as
described below.
DATA
POLLING: The AT49BV/LV16X(T) features Data Polling to indicate the end of a pro-
gram cycle. If the status configuration register is set to a “00”, during a program cycle an
attempted read of the last byte/word loaded will result in the complement of the loaded data on
I/O7. Once the program cycle has been completed, true data is valid on all outputs and the
next cycle may begin. During a chip or sector erase operation, an attempt to read the device
will give a “0” on I/O7. Once the program or erase cycle has completed, true data will be read
from the device. Data
Polling may begin at any time during the program cycle. Please see
“Status Bit Table” on page 12 for more details.
