ISL78302AARPLZ-T

1
DATASHEET
Dual LDO with Low Noise, Very High PSRR and Low I
Q
ISL78302A
ISL78302A is a high-performance dual LDO capable of
sourcing 300mA current from each output. It has a low
standby current and very high PSRR and is stable with output
capacitance of 1µF to 10µF with ESR of up to 200mΩ.
The device integrates an individual Power-On Reset (POR)
function for each output. The POR delay for VO2 can be
externally programmed by connecting a timing capacitor to the
CPOR pin. The POR delay for VO1 is internally fixed at
approximately 2ms. A reference bypass pin is also provided for
connecting a noise-filtering capacitor for low noise and
high-PSRR applications.
The quiescent current is typically only 47µA with both LDOs
enabled and active. Separate Enable pins control each
individual LDO output. When both Enable pins are low, the
device is in shutdown, typically drawing less than 0.3µA.
The ISL78302A is AEC-Q100 qualified. The ISL78302A is rated
for the automotive temperature range (-40°C to +105°C).
Features
Integrates Two 300mA High-performance LDOs
Excellent Transient Response to Large Current Steps
±1.8% Accuracy Over All Operating Conditions
Excellent Load Regulation: < 0.1% Voltage Change Across
Full Range of Load Current
Low Output Noise: Typically 30µV
RMS
at 100µA (1.5V)
Very High PSRR: 90dB at 1kHz
Extremely Low Quiescent Current: 47µA (Both LDOs Active)
Wide Input Voltage Capability: 2.3V to 6.5V
Low Dropout Voltage: Typically 230mV at 300mA
Stable with 1µF to 10µF Ceramic Capacitors
Separate Enable and POR Pins for Each LDO
Soft-start and Staged Turn-on to Limit Input Current Surge
During Enable
Current Limit and Overheat Protection
Tiny 10 Ld 3mmx3mm DFN Package
-40°C to +105°C Operating Temperature Range
Pb-free (RoHS Compliant)
AEC-Q100 Qualified
Applications
•Radio Receivers
Camera Modules
GPS/Navigation
•Infotainment Systems
C1, C4, C5: 1µF X5R CERAMIC CAPACITOR
C2: 0.1µF X7R CERAMIC CAPACITOR
ISL78302A
VIN
EN1
EN2
CBYP
CPOR
VO1
VO2
POR2
POR1
GND
10
9
8
7
6
1
2
3
4
5
VIN (2.3 TO 6.5V)
ENABLE1
ENABLE2
V
OUT1
V
OUT2
RESET1
RESET2
C1 C2 C3 C4 C5
C3: 0.01µF X7R CERAMIC CAPACITOR
OFF
ON
OFF
ON
(200ms DELAY,
C3 = 0.01µF)
(2ms DELAY)
V
OUT2
TOO LOW
V
OUT2
OK
V
OUT1
TOO LOW
V
OUT1
OK
FIGURE 1. TYPICAL APPLICATION
December 22, 2015
FN7932.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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ISL78302A
2
FN7932.2
December 22, 2015
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Block Diagram
VO2
LDO
ERROR
AMPLIFIER
IS1 1VQEN1
LDO-1
LDO-2
POR
COMPARATOR
VOK1
POR1
VREF
TRIM
VIN
VO1
VO2
POR2
POR1
GND
EN2
EN1
CONTROL
LOGIC
POR2
DELAY
POR1
DELAY
VOLTAGE
REFERENCE
GENERATOR
BANDGAP AND
TEMPERATURE
SENSOR
UVLO
VOK2
VOK1
1.00V
0.94V
0.90V
IS1
IS2
QEN1
QEN2
VO2
VO1
100k100k
CPOR
CBYP
VO1
~1.0V
VOK2
POR2
ISL78302A
3
FN7932.2
December 22, 2015
Submit Document Feedback
Pin Configuration
ISL78302A
(10 LD 3X3 DFN)
TOP VIEW
Pin Descriptions
PIN NUMBER PIN NAME TYPE DESCRIPTION
1 VIN Analog I/O Supply Voltage/LDO Input. Connect a 1µF capacitor to GND.
2 EN1 Low Voltage Compatible CMOS Input LDO-1 Enable
3 EN2 Low Voltage Compatible CMOS Input LDO-2 Enable
4 CBYP Analog I/O Reference Bypass Capacitor Pin. Optionally connect capacitor of value 0.01µF to 1µF
between this pin and GND to tune in the desired noise and PSRR performance.
5 CPOR Analog I/O POR2 Delay Setting Capacitor Pin. Connect a capacitor between this pin and GND to
delay the POR2
output release after LDO-2 output reaches 94% of its specified
voltage level (200ms delay per 0.01µF).
6 GND Ground Connection to system ground. Connect to PCB Ground plane.
7POR1
Open Drain Output (1mA) Open-drain POR Output for LDO-1 (active-low). Internally connected to VO1 through
100kΩ resistor.
8POR2
Open Drain Output (1mA) Open-drain POR Output for LDO-2 (active-low). Internally connected to VO2 through
100kΩ resistor.
9 VO2 Analog I/O LDO-2 Output. Connect capacitor of value 1µF to 10µF to GND
(1µF recommended).
10 VO1 Analog I/O LDO-1 Output. Connect capacitor of value 1µF to 10µF to GND
(1µF recommended).
VIN
EN1
EN2
CBYP
CPOR
VO1
VO2
POR2
POR1
GND
2
3
4
1
5
9
8
7
10
6
Ordering Information
PART NUMBER
(Notes 1
, 2, 3)
PART
MARKING
VO1 VOLTAGE
(V)
VO2 VOLTAGE
(V)
TEMP RANGE
(°C)
PACKAGE
(RoHS Compliant) PKG DWG. #
ISL78302AARMMZ DNAL 3.0 3.0 -40 to +105 10 Ld 3x3 DFN L10.3x3C
ISL78302AARLLZ DNAM 2.9 2.9 -40 to +105 10 Ld 3x3 DFN L10.3x3C
ISL78302AARJMZ DNAN 2.8 3.0 -40 to +105 10 Ld 3x3 DFN L10.3x3C
ISL78302AARJRZ DNAP 2.8 2.6 -40 to +105 10 Ld 3x3 DFN L10.3x3C
ISL78302AARJCZ DNAK 2.8 1.8 -40 to +105 10 Ld 3x3 DFN L10.3x3C
ISL78302AARGCZ DNAR 2.7 1.8 -40 to +105 10 Ld 3x3 DFN L10.3x3C
ISL78302AARPLZ DNAS 1.85 2.9 -40 to +105 10 Ld 3x3 DFN L10.3x3C
ISL78302AARBJZ DNAT 1.5 2.8 -40 to +105 10 Ld 3x3 DFN L10.3x3C
NOTES:
1. Add “-T” suffix for tape and reel. Please refer to TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL78302A
. For more information on MSL, please see Tech Brief TB363.

ISL78302AARPLZ-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
LDO Voltage Regulators ISL78302AARPLZ Autom Automotive Low Noise
Lifecycle:
New from this manufacturer.
Delivery:
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