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CAT824TTDI-GT3

P1-P3P4-P6P7-P9P10-P12
CAT823, CAT824, CAT825
http://onsemi.com
4
Table 3. ELECTRICAL OPERATING CHARACTERISTICS (DC Characteristics: V
CC
= 3.0 V to 5.5 V for L/M versions;
V
CC
= 2.0 V to 3.6 V for the R/S/T/U/Y/Z version, −40°C ≤ T
A
≤ +85°C unless otherwise noted. Typical Values at T
A
= 25°C and V
CC
= 5 V
for L/M versions; V
CC
= 3.3 V for the T/S versions; V
CC
= 3.0 V for the R version; and V
CC
= 2.5 V for the U/Y/Z versions.) (Note 1)
Symbol UnitsMaxTypMinConditionsParameter
WATCHDOG INPUT (CAT823 & CAT824)
t
WD
Watchdog Timeout Period 1.12 1.60 3.20 s
t
WDI
WDI Pulse Width V
IL
= 0.4 V, V
IH
= 0.8 x V
CC
50 ns
V
IL
WDI Input Voltage (Note 3)
0.3 x V
CC
V
V
IH
0.7 x V
CC
WDI Input Current (Note 4)
WDI = V
CC
, Time Average
120 160 mA
WDI = 0 V, Time Average −20 −15
MANUAL RESET INPUT (CAT823 & CAT825)
V
IL
MR Input Voltage
0.3 x V
CC
V
V
IH
0.7 x V
CC
t
PB
MR Pulse Width 1
ms
t
PDLY
MR low to Reset Delay 5
ms
MR Noise Immunity Pulse Width with No Reset 100 ns
MR Pullup Resistance
(internal)
35 52 75
kW
1. Over−temperature limits are guaranteed by design and not production tested.
2. The RESET short−circuit current is the maximum pull−up current when reset is driven low by a bidirectional output.
3. WDI is internally serviced within the watchdog period if WDI is left open.
4. The WDI input current is specified as an average input current when the WDI input is driven high or low. The WDI input if connected to
a three−stated output device can be disabled in the tristate mode as long as the leakage current is less than 10 mA and a maximum capacitance
of less than 200 pF. To clock the WDI input in the active mode the drive device must be able to source or sink at least 200 mA when active.
TYPICAL ELECTRICAL OPERATING CHARACTERISTICS
Figure 2. V
CC
Supply Current vs. Temperature Figure 3. Normalized Reset Threshold Voltage
vs. Temperature
TEMPERATURE (°C) TEMPERATURE (°C)
120806040200−20−40
1
2
3
4
6
7
8
9
100806040200−20−40
0.94
0.96
0.98
1.00
1.02
1.04
1.06
SUPPLY CURRENT (mA)
NORMALIZED RESET THRESHOLD (V)
100
5
CAT823, CAT824, CAT825
http://onsemi.com
5
FUNCTIONAL DESCRIPTION
Processor RESET
The CAT823−825 detect supply voltage (V
CC
) conditions
that are below the specified voltage trip value (V
RST
) and
provide a reset output to maintain correct system operation.
On power−up, RESET
(and RESET if available) are kept
active for a minimum delay t
RP
of 140 ms after the supply
voltage (V
CC
) rises above V
RST
to allow the power supply
and processor to stabilize. When V
CC
drops below the
voltage trip value (V
RST
), the reset output signals RESET
(and RESET) are pulled active. RESET (and RESET if
available) is specifically designed to provide the reset input
signals for processors. This provides reliable and consistent
operation as power is turned on, off or during brownout
conditions by maintaining the processor operation in known
conditions.
Manual RESET
The CAT823 and CAT825 each have a Manual Reset
(MR
) input to allow for alternative control of the reset
outputs. The MR
input is designed for direct connection to
a pushbutton (see Figure 4). The MR
input is internally
pulled up by 52 kW resistor and must be pulled low to cause
the reset outputs to go active. Internally, this input is
debounced and timed such that RESET (and RESET)
signals of at least 140 ms minimum will be generated. The
min 140 ms t
RP
delay commences as the Manual Reset input
is released from the low level. (see Figure 5)
RESET
CAT825
GND
Supply
Voltage
Figure 4. Pushbutton RESET
V
CC
MR
RESET
Figure 5. Timing Diagram – Pushbutton RESET
RESET
RESET
MR
V
IL
t
PDLY
t
PB
V
IH
t
RP
V
OH
V
OL
CAT823, CAT824, CAT825
http://onsemi.com
6
Watchdog Timer
The CAT823 and CAT824 provide a Watchdog input
(WDI). The watchdog timer function forces RESET
(and
RESET in the CAT824) signals active when the WDI input
does not have a transition from low−to−high or high−to−low
within 1.12 seconds. Timeout of the watchdog starts when
RESET
(RESET on the CAT824) becomes inactive. If a
transition occurs on the WDI input pin prior to the watchdog
time−out, the watchdog timer is reset and begins to time−out
again. If the watchdog timer is allowed to time−out, then the
reset output(s) will go active for t
RP
and once released will
repeat the watchdog timeout process.
Figure 6 below shows a typical implementation of a
watchdog function. Any processor signal that repeats
dependant on the normal operation of the processor or
directed by the software operating on the processor can be
used to strobe the watchdog input. The most reliable is a
dedicated I/O output transitioned by a specific software
instruction.
The watchdog can be disabled by floating (or tri−stating)
the WDI input (see Figure 7). If the watchdog is disabled the
WDI pin will be pulled low for the first 7/8
th
’s of the
watchdog period (t
WD
) and pulled high for the last 1/8
th
of
the watchdog period. This pulling low of the WDI input and
then high is used to detect an open or tri−state condition and
will continue to repeat until the WDI input is driven high or
low.
For most efficient operation of devices with the watchdog
function the WDI input should be held low the majority of
the time and only strobed high as required to reset the
watchdog timer.
Figure 6. Watchdog Timer
CAT823
PIC
μC
DECODER
ADDRESS
GND
WDI
Supply
Voltage
V
CC
RESET
MR
MCLR
Figure 7. Watchdog Disable Circuit
mC
OUTPUT
Tristate
150 kW
CAT823
GND
WDI
MR
RESET
110 kW
V
CC
V
CC
Figure 8. Timing Diagram – Strobe Input
WDI
INVALID
STROBE
VALID
STROBE
MIN.
MAX.
INDETERMINATE
STROBE
RESET
t
WD
P1-P3P4-P6P7-P9P10-P12

CAT824TTDI-GT3

Mfr. #:
Buy CAT824TTDI-GT3
Manufacturer:
ON Semiconductor
Description:
IC SUPERVISOR MPU 3.08V TSOT23-5
Lifecycle:
New from this manufacturer.
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