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74HCT08DR2G

P1-P3P4-P6P7-P7
© Semiconductor Components Industries, LLC, 2009
May, 2009 − Rev. 2
1 Publication Order Number:
74HCT08/D
74HCT08
Quad 2-Input AND Gate
With LSTTL−Compatible Inputs
High−Performance Silicon−Gate CMOS
The 74HCT08 is identical in pinout to the LS08. The device has
TTL−compatible inputs.
Features
• Output Drive Capability: 10 LSTTL Loads
• TTL/NMOS−Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With the JEDEC Standard No. 7A Requirements
• ESD Performance: HBM > 2000 V; Machine Model > 200 V
• Chip Complexity: 24 FETs or 6 Equivalent Gates
• These are Pb−Free Devices
3
Y1
1
A1
PIN 14 = V
CC
PIN 7 = GND
LOGIC DIAGRAM
2
B1
6
Y2
4
A2
5
B2
8
Y3
9
A3
10
B3
11
Y4
12
A4
13
B4
Y = AB
Pinout: 14−Lead Packages (Top View)
1314 12 11 10 9 8
21 34567
V
CC
B4 A4 Y4 B3 A3 Y3
A1 B1 Y1 A2 B2 Y2 GND
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MARKING
DIAGRAMS
HCT08 = Device Code
A = Assembly Location
WL or L = Wafer Lot
Y = Year
WW or W = Work Week
G or G = Pb−Free Package
TSSOP−14
DT SUFFIX
CASE 948G
14
1
SOIC−14
D SUFFIX
CASE 751A
14
1
HCT08G
AWLYWW
1
14
HCT
08
ALYW G
G
1
14
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
L
L
H
H
L
H
L
H
FUNCTION TABLE
Inputs Output
AB
L
L
L
H
Y
(Note: Microdot may be in either location)
74HCT08
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2
ORDERING INFORMATION
Device Package Shipping
†
74HCT08DR2G SOIC−14
(Pb−Free)
2500/Tape & Reel
74HCT08DR2GH SOIC−14
(Halide−Free)
74HCT08DTR2G TSSOP−14*
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V
V
in
DC Input Voltage (Referenced to GND) – 0.5 to + 7.0 V
V
out
DC Output Voltage (Referenced to GND) – 0.5 to V
CC
+ 0.5 V
I
in
DC Input Current, per Pin ±20 mA
I
out
DC Output Current, per Pin ±25 mA
I
CC
DC Supply Current, V
CC
and GND Pins ±50 mA
P
D
Power Dissipation in Still Air, SOIC Package†
TSSOP Package†
500
450
mW
T
stg
Storage Temperature – 65 to + 150
_C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
SOIC or TSSOP Package
260
_C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage (Referenced to GND) 4.5 5.5 V
V
in
DC Input Voltage (Referenced to GND) 0 5.5 V
V
out
DC Output Voltage (Referenced to GND) 0 V
CC
V
T
A
Operating Temperature, All Package Types −55 +125
_C
t
r
, t
f
Input Rise and Fall Time V
CC
= 2.0 V
(Figure 1) V
CC
= 4.5 V
V
CC
= 6.0 V
0
0
0
1000
500
400
ns
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
74HCT08
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3
DC CHARACTERISTICS (Voltages Referenced to GND)
V
CC
(V)
Guaranteed Limit
Symbol Parameter Condition −55 to 25°C ≤85°C ≤125°C Unit
V
IH
Minimum High−Level Input Voltage V
out
= 0.1V
|I
out
| ≤ 20mA
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
V
IL
Maximum Low−Level Input Voltage V
out
= V
CC
− 0.1V
|I
out
| ≤ 20mA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
V
OH
Minimum High−Level Output
Voltage
V
in
= V
IL
|I
out
| ≤ 20mA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
V
in
= V
IL
|I
out
| ≤ 4.0mA 4.5 3.98 3.84 3.70
V
OL
Maximum Low−Level Output
Voltage
V
in
= V
IH
|I
out
| ≤ 20mA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IH
|I
out
| ≤ 4.0mA 4.5 0.26 0.33 0.40
I
in
Maximum Input Leakage Current V
in
= V
CC
or GND 5.5 ±0.1 ±1.0 ±1.0
mA
I
CC
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
I
out
= 0mA
5.5 2.0 20 40
mA
DI
CC
Additional Quiescent Supply
Current
V
in
= 2.4V, Any One Input
V
in
= V
CC
or GND, Other Inputs
I
out
= 0mA
5.5
≥ −55°C 25 to 125°C
mA
2.9 2.4
1. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
2. Total Supply Current = I
CC
+ ΣDI
CC
.
AC CHARACTERISTICS (C
L
= 50pF, Input t
r
= t
f
= 6ns)
V
CC
(V)
Guaranteed Limit
Symbol Parameter −55 to 25°C ≤85°C ≤125°C Unit
t
PLH
,
t
PHL
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)
4.5 15 19 22 ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
4.5 15 19 22 ns
C
in
Maximum Input Capacitance 10 10 10 pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
C
PD
Power Dissipation Capacitance (Per Buffer)*
Typical @ 25°C, V
CC
= 5.0 V, V
EE
= 0 V
pF
20
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC
2
f + I
CC
V
CC
. For load considerations, see Chapter 2 of the
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
P1-P3P4-P6P7-P7

74HCT08DR2G

Mfr. #:
Buy 74HCT08DR2G
Manufacturer:
ON Semiconductor
Description:
Logic Gates QUAD 2 INPT AND GATE
Lifecycle:
New from this manufacturer.
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