5
Speci cations and content subject to change without prior noti cation.
HFBR-2506AFZ Receiver
The HFBR-2506AFZ receiver is housed in a metal pack-
age, consisting of a silicon PIN photodiode and digitizing
IC to produce a logic compatible output. The IC includes
a unique circuit to correct the pulse width distortion of
the rst bit after a long idle period. This enables opera-
tion from DC to 16MBd with low PWD for arbitrary data
patterns.
The receiver is a “push-pull” stage compatible with TTL
and CMOS logic. The HFBR-2506AFZ is compatible with
SMA connectors.
Figure 6.
Absolute Maximum Ratings
Parameter Symbol Min Max Unit Notes
Storage and Operating Temperature T
S
,
O
-40 +85 °C
Supply Voltage V
CC
-0.5 5.5 V
Average Output Current I
O
,
AVG
16 mA
Output Power Dissipation P
OD
80 mW
Lead Soldering Cycle
Temp
Time
T
SOL
T
SOL
260
10
°C
s
1, 5
Electrical Characteristics Table
-40 °C to +85 °C, 4.75 V < V
CC
< 5.25 V, V
P-P
Noise < = 100 mV unless otherwise noted.
Parameter Symbol Min Typ Max Unit Condition Notes
Peak Input Power Level Logic HIGH P
RH
-42
-44
dBm 1 mm POF
200 μm HCS
2
Peak Input Power Level Logic LOW P
RL
-20
-22
-2
-10
dBm 1 mm POF
200 μm HCS
|PWD| < 19 ns
3
Supply Current I
CC
19 45 mA V
O
= Open
High Level Output Voltage V
OH
4.2 4.7 V I
O
= 40 μA
Low Level Output Voltage V
OH
0.22 0.4 V I
O
= 1.6 mA
Pulse Width Distortion PWD -19 19 ns
Propagation Delay Time T
P_HL
or
_LH
150 ns
Notes:
1. 1.6 mm below seating plane.
2. Typical data are at +25 °C, V
CC
= 5.0 V
3. BER <= 10E
-9
, includes a 10.8 dB margin below the receiver switching threshold level (signal to noise ratio =12)
4. Pins 1 and 4 are electrically connected to the metal housing and are also used for mounting and retaining purposes. It is recommended that
pins 1 and 4 to be connected to ground to maintain housing shield e ectiveness.
5. Moisture sensitivity level (MSL) is 3
PIN FUNCTION
1
4
5
6
7
8
CONNECTED TO PIN 4
CONNECTED TO PIN 1
NO CONNECT
VCC
GND
VO
5
6
7
8
4
1
BOTTOM VIEW,
HFBR-2506AFZ
SEE NOTE 4
