LT3439EFE#PBF

7
LT3439
sn3439 3439fs
Oscillator SYNC
The oscillator can be synchronized to an external clock.
Set the RC timing components for an oscillator frequency
10% below the desired sync frequency.
It is recommended that the SYNC pin be driven with a
square wave that has an amplitude greater than 2V, a pulse
width greater than 1µs and a rise time less than 500ns. The
rising edge of the sync waveform triggers the change in
the state of the outputs.
Slew Rate Setting
Setting the LT3439 maximum slew rate is easy. The
external resistor to ground on the R
SL
pin sets the maxi-
mum slew rate. To determine the maximum slew rate
connect a 50k resistor pot with a 3.4k series resistance to
the R
SL
pin. Start at the lowest resistance setting and
increase the pot until the noise level meets your require-
ments. Note that slower slewing waveforms will lower the
power supply efficiency. Consult Linear Technology Appli-
cation Note 70, “A Monolithic Switching Regulator with
100µV Output Noise” for recommended noise measure-
ment techniques.
Shutdown
The SHDN pin is used to shut down the part. Grounding
this pin will disable all internal circuitry.
Increasing the SHDN voltage above the turn-on threshold,
approximately 1.3V, will enable the part. At the turn-on
threshold approximately 20µA of current is sourced out of
the pin. This current, in conjunction with the Thevenin
resistance on the pin, sets up the amount of hysteresis.
This allows the user to set the turn-on voltage of the supply
and the start-up hysteresis with a resistor divider. The
hysteresis can be used to prevent the part from shutting
down due to input voltage sag from an initial high current
draw. When the SHDN pin is greater than 2.1V, the
hysteresis current is reduced to zero.
In addition to the current hysteresis, there is also approxi-
mately 35mV of voltage hysteresis on the SHDN pin.
If a resistor divider is used to set the turn on threshold the
resistors are determined by the following equations:
APPLICATIO S I FOR ATIO
WUUU
V
RR
R
V
ON
AB
B
SHDN
=
+
SHDN
R
A
R
B
3439 AI01
V
IN
V
ON
is the input voltage at which the supply will turn on and
V
SHDN
is the SHDN pin turn-on threshold, typically 1.3V.
VR
V
RR
I
HYST A
SHDN
AB
SHDN
=
+
||
V
HYST
is the actual hysteresis voltage seen at the input
voltage. I
SHDN
is the current hysteresis sourced by the IC
at the turn-on threshold, typically 20µA. V
SHDN
is the
voltage hysteresis seen at the SHDN pin at the turn-on
threshold, typically 35mV.
The resistors can be calculated as follows:
R
VV VV
IV
R
VV VV
IVV
A
HYST
SHDN
ON
SHDN
SHDN SHDN
B
HYST
SHDN
ON
SHDN
SHDN
ON
SHDN
=
()
=
()
()
•–
•–
•–
For example if the turn-on voltage was to be set at 5V with
0.5V of hysteresis:
R
VVVmV
AV
k
R
VVVmV
AV V
k
A
B
=
()
µ
=
=
()
µ
()
=
05 13 5 35
20 1 3
18 27
05 13 5 35
20 5 1 3
642
.•.–
•.
.
.•.–
•–.
.
The nearest 1% values would be 18.2k and 6.49k.
A resistor in series with the SHDN pin could further change
hysteresis without changing the turn-on voltage.
Thermal Considerations
Decreasing the noise by lowering the slew rate of the
output switches does not come for free. Lower slew rates
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LT3439
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mean greater switching losses in the internal output
switches. However, efficiency is only modestly reduced
for a large improvement in EMI.
Care should be taken to ensure that the worst-case input
voltage and load current conditions do not cause an
excessive die temperature. The total power dissipation of
the IC is dominated by three loss terms, regulator losses,
saturation losses and switching losses. The following
formulas may be used to approximate these losses:
1. Regulator Dissipation:
PVmA
I
VIN IN
=+
12
60
where I is the average switch current.
2. Switch Saturation Dissipation:
P
VSAT
= (V
SAT
)(I)
3. Switch Switching Dissipation:
PVIf
I
R
V
R
SW IN OSC
SL
SL
=
+
()
+
+
()
10
2 3 10 10 8
1 7 10 65 8
6
4
3
••
–. .
–. .
Total IC power dissipation (P
D
) is the sum of these three
terms. Die junction temperature can be computed as
follows:
T
J
= T
AMB
+ (P
D
)(θ
JA
)
where T
AMB
is the ambient temperature, T
J
is the junction
temperature and θ
JA
is the thermal resistance from junc-
tion to ambient.
The LT3439 comes in the 16-pin TSSOP with exposed
backside package that has a very low junction-to-ambient
thermal resistance (θ
JA
) of approximately 40°C/W.
Transformer Design
Table 1 lists recommended center tapped transformers for
a variety of input voltage, output voltage and power
combinations.
These transformers will yield slightly high output voltages
so that they can accommodate an LDO regulator on the
output.
If your application is not listed, the LTC Applications group
is available to assist in the choice and/or the design of the
transformer.
In the design/selection of the transformer the following
characteristics are critical and should be considered.
Turns Ratio
The turns ratio of the transformer determines the output
voltage. The following equation can be used as a first pass
to calculate the turns ratio:
N
N
VV
VV
S
P
OUT F
IN SW
=
+
where V
F
is the forward voltage of the output diode and
V
SW
is the voltage drop across the internal switches (see
Typical Performance curves).
Sufficient margin should be added to the turns ratio to
account for voltage drops due to transformer winding
resistances. Also, if using an LDO for regulating the output
voltage, don’t forget to take into account the voltage drop
that should be added to V
OUT
.
Magnetizing Current
The primary inductance of the transformer causes a ripple
current that is independent of load current. The ripple
current manifests itself in the output voltage through the
parasitic resistances of the supply. Increasing the trans-
former magnetizing inductance can reduce the ripple
Table 1
NOMINAL NOMINAL
INPUT OUTPUT OUTPUT COILTRONICS
VOLTAGE VOLTAGE POWER PART NUMBER
5V 12V 1.5W CTX02-13716-X1
5V 12V 3.0W CTX02-13665-X1
5V ±15V 1.5W CTX02-13713-X1
5V ±15V 3.0W CTX02-13664-X1
5V 12V 1.5W CTX02-13834-X3
5V 12V 10W CTX02-13949-X1
12V 12V 6W CTX02-16076
9
LT3439
sn3439 3439fs
APPLICATIO S I FOR ATIO
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current. This can be accomplished by adding more turns
onto a given core or selecting a new core with a higher
inductance per turn squared characteristic (A
L
).
The following equation can be used to set the transformer
primary inductance:
LV
t
I
PRI IN
ON
=
t
ON
can be calculated by 1/f
OSC
.
I is somewhat arbitrary but a general rule of thumb is to
set it between 10% to 30% of I
PRI
where I
PRI
is calculated
as follows:
I
VI
V Eff
PRI
OUT OUT
IN
=
Eff can be estimated at 70%.
Winding Resistance
Resistance in either the primary or secondary winding will
reduce overall efficiency and degrade load regulation. If
efficiency or load regulation is unsatisfactory, verify that
the voltage drops in the transformer windings are not
excessive.
Leakage Inductance
When the output switches turn off, the transformer leak-
age inductance causes a voltage spike on the output
switch collector. The size of the voltage spike is propor-
tional to the magnitude of the leakage inductance and to
the square of the load current (energy stored in the leakage
inductance). The voltage spike should be limited so that it
does not exceed the voltage breakdown of the output
switches. This can be accomplished by reducing the
transformer’s leakage inductance or by reducing the maxi-
mum slew rate. The voltage slew control will limit the
voltage spike by dissipating the leakage energy in the
power switches.
Transformer Imbalance
A common concern for the push-pull topology is trans-
former imbalance. If the volt/second products of each half
of the switching cycle do not match, the transformer’s flux
level walks up the BH curve and the transformer goes into
saturation. This is undesirable because the effective mag-
netizing inductance drops off and the magnetizing current
increases rapidly. Fortunately, there are parasitics in the
circuit that counteract the transformer saturation. When
the transformer begins to saturate the magnetizing cur-
rent increases in one half of the switching cycle and
therefore, the IR drops increase thereby reducing the volt/
second product of that half cycle. The transformer balance
is maintained. Also, the losses in the transformer and the
main switches have positive temperature coefficients elimi-
nating the potential for thermal runaway. The LT3439 can
compensate for small circuit imbalances, however care
should be taken to balance both sides of the circuit
including transformer design and PCB layout.
Transformer Design Example
The following is an example of the design of a DC trans-
former for a 5V to 5V at 500mA supply.
Supply specs: V
IN
= 5V, V
OUT
= 5V, I
OUT
= 500mA,
f
OSC
= 100kHz
Assume: V
F
= 0.5V (forward voltage of output diode)
Efficiency 70%
Calculate the primary switch current (I
PRI
):
I
VI
V Eff
VmA
V
A
PRI
OUT OUT
IN
== =
••
•%
.
5 500
570
0 714
The “Switch Voltage Drop vs Switch Current” Typical
Performance curve gives a typical value of the switch
voltage drop (V
SW
) for a given switch current (I
PRI
). In this
example, I
PRI
0.7A, therefore V
SW
0.5V.
Next, calculate the turns ratio:
N
N
VV
VV
VV
VV
S
P
OUT F
IN SW
=
+
=
+
=
.
–.
.
505
505
122
Add 15% margin to account for winding resistance of the
transformer:
N
N
S
P
=+=122 15 141.%.

LT3439EFE#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators SR Controlled Ultralow N 1A Iso DC/DC Tr
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