1. General description
The 74LVC16374A and 74LVCH16374A are 16-bit edge-triggered flip-flops featuring
separate D-type inputs with bus hold (74LVCH16374A only) for each flip-flop and 3-state
outputs for bus oriented applications. It consists of two sections of eight positive
edge-triggered flip-flops. A clock input (nCP) and an output enable (nOE
) are provided for
each octal.
The flip-flops will store the state of their individual D-inputs that meet the set-up and hold
time requirements on the LOW-to-HIGH clock (CP) transition.
When pin nOE
is LOW, the contents of the flip-flops are available at the outputs. When pin
nOE
is HIGH, the outputs go to the high-impedance OFF-state. Operation of input nOE
does not affect the state of the flip-flops.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices in mixed 3.3 V and
5 V applications.
Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused
inputs.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Multibyte flow-through standard pin-out architecture
Low inductance multiple supply pins for minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold (74LVCH16374A only)
High-impedance outputs when V
CC
= 0 V
Complies with JEDEC standard JESD8-B/JESD36
ESD protection:
HBM JESD22-A114F exceeds 2000 V
CDM JESD22-C101D exceeds 1000 V
Specified from −40 °C to +85 °C and −40 °C to +125 °C
74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop with 5 V tolerant
inputs/outputs; 3-state
Rev. 07 — 23 March 2010 Product data sheet
