12
LT1640L/LT1640H
1640lhfb
The new threshold voltage when the input moves from low
to high is:
VV
R R RR RR
RR
UV LH UVH,
•••
•
=
++
23 13 12
23
where V
UVH
is typically 1.243V.
The new threshold voltage when the input moves from
high to low is:
VV
R R RR RR
RR
V
R
R
UV HL UVL GATE,
•••
•
–•=
++
23 13 12
23
1
3
where V
UVL
is typically 1.223V.
The new hysteresis value will be:
VV
R R RR RR
RR
V
R
R
HYS UVHY GATE
=
++
+
23 13 12
23
1
3
•••
•
•
With R1 = 562k, R2 = 16.9k and R3 = 1.62M, V
GATE
= 13.5V
and V
UVHY
= 20mV, the undervoltage threshold will be 43V
(from low to high) and 37.6V (from high to low). The
hysteresis is 5.4V. A separate resistor divider should be
used to set the overvoltage threshold given by:
APPLICATIONS INFORMATION
WUU
U
VV
RR
R
OV OVH
=
+
45
5
With R4 = 506k, R5 = 8.87k and V
OVH
= 1.223V, the
overvoltage threshold will be 71V.
PWRGD/PWRGD Output
The PWRGD/PWRGD output can be used to directly en-
able a power module when the input voltage to the module
is within tolerance. The LT1640L has a PWRGD output for
modules with an active low enable input, and the LT1640H
has a PWRGD output for modules with an active high
enable input.
When the DRAIN voltage of the LT1640H is high with
respect to V
EE
(Figure 11), the internal transistor Q3 is
turned off and R7 and Q2 clamp the PWRGD pin one diode
drop (≈0.7V) above the DRAIN pin. Transistor Q2 sinks
the module’s pull-up current and the module turns off.
When the DRAIN voltage drops below V
PG
, Q3 will turn on,
shorting the bottom of R7 to DRAIN and turning Q2 off.
The pull-up current in the module then flows through R7,
pulling the PWRGD pin high and enabling the module.
+
V
EE
V
DD
LT1640H
SENSE
C1
C3
Q1
R2
R3
C2
R4
R5
R6
R1
4
3
2
OV
GND
–48V
UV
56
8
1
7
GATE
1640 F11
PWRGD
DRAIN
V
EE
R7
6.5k
Q2
–
+
V
PG
Q3
ACTIVE HIGH
ENABLE MODULE
V
OUT
+
V
OUT
–
V
IN
+
V
IN
–
ON/OFF
GND
(SHORT PIN)
*
* DIODES INC. SMAT70A
2× 1N4148
43
21
+
–
Figure 11. Active High Enable Module
