AD9985KSTZ-110 Datasheet AD9985AKSTZ-110, AD9985ABSTZ-110, AD9985KSTZ-110 | P22-P24

AD9985

Rev. 0 | Page 21 of 32

MODE CONTROL 1

0E 7 Hsync Input Polarity Override

This register is used to override the internal circuitry

that determines the polarity of the Hsync signal going

into the PLL.

Table 13. Hsync Input Polarity Override Settings

Override Bit Function

0 Hsync Polarity Determined by Chip

1 Hsync Polarity Determined by User

The default for Hsync polarity override is 0 (polarity

determined by chip).

0E 6 HSPOL Hsync Input Polarity

A bit that must be set to indicate the polarity of the

Hsync signal that is applied to the PLL Hsync input.

Table 14. Hsync Input Polarity Settings

HSPOL Function

0 Active Low

1 Active High

Active Low means the leading edge of the Hsync pulse

is negative going. All timing is based on the leading

edge of Hsync, which is the falling edge. The rising

edge has no effect.

Active high is inverted from the traditional Hsync,

with a positive-going pulse. This means that timing

will be based on the leading edge of Hsync, which is

now the rising edge.

The device will operate if this bit is set incorrectly, but

the internally generated clamp position, as established

by Clamp Placement (Register 05H), will not be

placed as expected, which may generate clamping

errors.

The power-up default value is HSPOL = 1.

0E 5 Hsync Output Polarity

This bit determines the polarity of the Hsync output

and the SOG output. Table 15 shows the effect of this

option. SYNC indicates the logic state of the sync

pulse.

Table 15. Hsync Output Polarity Settings

Setting SYNC

0 Logic 1 (Positive Polarity)

1 Logic 0 (Negative Polarity)

The default setting for this register is 0.

0E 4 Active Hsync Override

This bit is used to override the automatic Hsync

selection, To override, set this bit to Logic 1. When

overriding, the active Hsync is set via Bit 3 in this

Table 16. Active Hsync Override Settings

Override Result

0 Autodetermines the Active Interface

1 Override, Bit 3 Determines the Active Interface

The default for this register is 0.

0E 3 Active Hsync Select

This bit is used under two conditions. It is used to

select the active Hsync when the override bit is set

(Bit 4). Alternately, it is used to determine the active

Hsync when not overriding but both Hsyncs are

detected.

Table 17. Active HSYNC Select Settings

Select Result

0 HSYNC Input

1 Sync-on-Green Input

The default for this register is 0.

0E 2 Vsync Output Invert

This bit inverts the polarity of the Vsync output.

Table 18 shows the effect of this option.

Table 18. Vsync Output Invert Settings

Setting Vsync Output

0 Invert

1 No Invert

The default setting for this register is 0.

0E 1 Active Vsync Override

This bit is used to override the automatic Vsync

selection. To override, set this bit to Logic 1. When

overriding, the active interface is set via Bit 0 in this

Table 19. Active Vsync Override Settings

Override Result

0 Autodetermines the Active Vsync

1 Override, Bit 0 Determines the Active Vsync

The default for this register is 0.

0E 0 Active Vsync Select

This bit is used to select the active Vsync when the

override bit is set (Bit 1).

Table 20. Active Vsync Select Settings

Select Result

0 Vsync Input

1 Sync Separator Output

The default for this register is 0.

AD9985

Rev. 0 | Page 22 of 32

0F 7 Clamp Input Signal Source

This bit determines the source of clamp timing.

Table 21. Clamp Input Signal Source Settings

Clamp Function Function

0 Internally Generated Clamp Signal

1 Externally Provided Clamp Signal

A 0 enables the clamp timing circuitry controlled by

clamp placement and clamp duration. The clamp

position and duration is counted from the leading

edge of Hsync.

A 1 enables the external CLAMP input pin. The three

channels are clamped when the CLAMP signal is

active. The polarity of CLAMP is determined by the

Clamp Polarity bit (Register 0FH, Bit 6).

The power-up default value is Clamp Function = 0.

0F 6 Clamp Input Signal Polarity

This bit determines the polarity of the externally

provided CLAMP signal.

Table 22. Clamp Input Signal Polarity Settings

Clamp Function Function

1 Active Low

0 Active High

Logic 1 means that the circuit will clamp when

CLAMP is low, and it will pass the signal to the ADC

when CLAMP is high.

Logic 0 means that the circuit will clamp when

CLAMP is high, and it will pass the signal to the ADC

when CLAMP is low.

The power-up default value is Clamp Polarity = 1.

0F 5 Coast Select

This bit is used to select the active Coast source. The

choices are the Coast Input pin or Vsync. If Vsync is

selected, the additional decision of using the Vsync

input pin or the output from the sync separator needs

to be made (Register 0E, Bits 1, 0).

Table 23. Power-Down Settings

Select Result

0 Coast Input Pin

1 Vsync (See above Text)

0F 4 Coast Input Polarity Override

This register is used to override the internal circuitry

that determines the polarity of the Coast signal going

into the PLL.

Table 24. Coast Input Polarity Override Settings

Override Bit Result

0 Determined by Chip

1 Determined by User

The default for coast polarity override is 0.

0F 3 Coast Input Polarity

This bit indicates the polarity of the Coast signal that

is applied to the PLL COAST input.

Table 25. Coast Input Polarity Settings

Coast Polarity Function

0 Active Low

1 Active High

Active Low means that the clock generator will ignore

Hsync inputs when Coast is low, and continue

operating at the same nominal frequency until Coast

goes high.

Active High means that the clock generator will ignore

Hsync inputs when Coast is high, and continue

operating at the same nominal frequency until Coast

goes low.

This function needs to be used along with the Coast

Polarity Override bit (Bit 4).

The power-up default value is 1.

0F 2 Seek Mode Override

This bit is used to either allow or disallow the low

power mode. The low power mode (Seek Mode)

occurs when there are no signals on any of the Sync

inputs.

Table 26. Seek Mode Override Settings

Select Result

1 Allow Seek Mode

0 Disallow Seek Mode

The default for this register is 1.

0F 1

PWRDN

This bit is used to put the chip in full power-down. See

the Power Management section for details of which

blocks are powered down.

Table 27. Power-Down Settings

Select Result

0 Power-Down

1 Normal Operation

10 7-3 Sync-on-Green Slicer Threshold

This register allows the comparator threshold of the

Sync-on-Green slicer to be adjusted. This register

adjusts it in steps of 10 mV, with the minimum setting

equaling 10 mV (11111) and the maximum setting

equaling 330 mV (00000).

The default setting is 23, which corresponds to a

threshold value of 100 mV; for a threshold of 150 mV,

the setting should be 18.

AD9985

Rev. 0 | Page 23 of 32

10 2 Red Clamp Select

This bit determines whether the Red channel is

clamped to ground or to midscale. For RGB video, all

three channels are referenced to ground. For YCbCr

(or YUV), the Y channel is referenced to ground, but

the CbCr channels are referenced to midscale.

Clamping to midscale actually clamps to Pin 37.

Table 28. Red Clamp Select Settings

Clamp Function

0 Clamp to Ground

1 Clamp to Midscale (Pin 37)

The default setting for this register is 0.

10 1 Green Clamp Select

This bit determines whether the Green channel is

clamped to ground or to midscale.

Table 29. Green Clamp Select Settings

Clamp Function

0 Clamp to Ground

1 Clamp to Midscale (Pin 37)

The default setting for this register is 0.

10 0 Blue Clamp Select

This bit determines whether the Blue channel is

clamped to ground or to midscale.

Table 30. Blue Clamp Select Settings

Clamp Function

0 Clamp to Ground

1 Clamp to Midscale (Pin 37)

The default for this register is 0.

11 7–0 Sync Separator Threshold

This register is used to set the responsiveness of the

sync separator. It sets how many internal 5 MHz clock

periods the sync separator must count to before

toggling high or low. It works like a low-pass filter to

ignore Hsync pulses in order to extract the Vsync

signal. This register should be set to some number

greater than the maximum Hsync pulsewidth. Note

that the sync separator threshold uses an internal

dedicated clock with a frequency of approximately

5 MHz.

The default for this register is 32.

12 7–0 Pre-Coast

This register allows the coast signal to be applied prior

to the Vsync signal. This is necessary in cases where

pre-equalization pulses are present. The step size for

this control is one Hsync period.

The default is 0.

13 7–0 Post-Coast

This register allows the coast signal to be applied

following the Vsync signal. This is necessary in cases

where post-equalization pulses are present. The step

size for this control is one Hsync period.

The default is 0.

14 7 Hsync Detect

This bit is used to indicate when activity is detected on

the Hsync input pin (Pin 30). If Hsync is held high or

low, activity will not be detected.

Table 31. Hsync Detection Results

Detect Function

0 No Activity Detected

1 Activity Detected

The Sync Processing Block Diagram (Figure 14) shows

where this function is implemented.

14 6 AHS – Active Hsync

This bit indicates which Hsync input source is being

used by the PLL (Hsync input or Sync-on-Green).

Bits 7 and 1 in this register determine which source is

used. If both Hsync and SOG are detected, the user

can determine which has priority via Bit 3 in

Bit 4 in Register 0EH. If the override bit is set to

Logic 1, this bit will be forced to whatever the state of

Bit 3 in Register 0EH is set to.

Table 32. Active Hsync Results

Bit 7 Bit 1 Bit 4,

(Hsync (SOG Reg 0EH

Detect) Detect) (Override) AHS

0 0 0 Bit 3 in 0EH

0 1 0 1

1 0 0 0

1 1 0 Bit 3 in 0EH

X X 1 Bit 3 in 0EH

AHS = 0 means use the Hsync pin input for Hsync.

AHS = 1 means use the SOG pin input for Hsync.

The override bit is in Register 0EH, Bit 4.

14 5 Detected Hsync Input Polarity Status

This bit reports the status of the Hsync input polarity

detection circuit. It can be used to determine the

polarity of the Hsync input. The detection circuit’s

location is shown in the Sync Processing Block

Diagram (Figure 14).

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33

AD9985KSTZ-110

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Manufacturer:

Analog Devices Inc.

Description:

Display Interface IC 110 MSPS Analog IF

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AD9985KSTZ-110

AD9985KSTZ-110

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