AD9650USVZR7-105EP Datasheet AD9650USVZ-105EP, AD9650USVZR7-105EP | P7-P9

Data Sheet AD9650-EP

Rev. 0 | Page 7 of 12

Timing Diagrams

SKEW

DCO

CLK

N – 12N – 13

N – 1

N + 1

N + 2

N + 3

N + 5

N + 4

N – 11 N – 10 N – 9 N – 8

CLK+

CLK–

CH A/CH B DATA

DCOA/DCOB

11312-002

Figure 2. CMOS Default Output Mode Data Output Timing

SKEW

DCO

CLK

CH A

N – 12

CH B

N – 12

CH A

N – 11

CH B

N – 11

CH A

N – 10

CH B

N – 10

CH A

N – 9

CH B

N – 9

CH A

N – 8

N – 1

N + 1

N + 2

N + 3

N + 5

N + 4

CLK+

CLK–

CH A/CH B DATA

DCOA/DCOB

11312-003

Figure 3. CMOS Interleaved Output Mode Data Output Timing

SKEW

DCO

CLK

CH A

N – 12

CH B

N – 12

CH A

N – 11

CH B

N – 11

CH A

N – 10

CH B

N – 10

CH A

N – 9

CH B

N – 9

CH A

N – 8

N – 1

N + 1

N + 2

N + 3

N + 5

N + 4

CLK+

CLK–

CH A/CH B DATA

DCO+/DCO–

11312-004

Figure 4. LVDS Mode Data Output Timing

SYNC

CLK+

HSYNC

SSYNC

11312-005

Figure 5. SYNC Input Timing Requirements

AD9650-EP Data Sheet

Rev. 0 | Page 8 of 12

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

Electrical

AVDD to AGND

−0.3 V to +2.0 V

DRVDD to AGND −0.3 V to +2.0 V

VIN+A/VIN+B, VIN−A/VIN−B

to AGND

−0.3 V to AVDD + 0.2 V

CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V

SYNC to AGND −0.3 V to AVDD + 0.2 V

VREF to AGND

−0.3 V to AVDD + 0.2 V

SENSE to AGND −0.3 V to AVDD + 0.2 V

VCM to AGND −0.3 V to AVDD + 0.2 V

RBIAS to AGND −0.3 V to AVDD + 0.2 V

CSB to AGND −0.3 V to DRVDD + 0.2 V

SCLK/DFS to AGND −0.3 V to DRVDD + 0.2 V

SDIO/DCS to AGND −0.3 V to DRVDD + 0.2 V

OEB −0.3 V to DRVDD + 0.2 V

PDWN −0.3 V to DRVDD + 0.2 V

D0+/D0− Through D15+/D15−

to AGND

−0.3 V to DRVDD + 0.2 V

DCO+/DCO− to AGND

−0.3 V to DRVDD + 0.2 V

Environmental

Operating Temperature Range

(Ambient)

−55°C to +85°C

Maximum Junction Temperature

Under Bias

150°C

Storage Temperature Range

(Ambient)

−65°C to +150°C

The inputs and outputs are rated to the supply voltage (AVDD + 0.2 V or

DRVDD + 0.2 V), but they should not exceed 2.1 V.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

THERMAL CHARACTERISTICS

The exposed pad on the underside of the TQFP package must

be soldered to the ground plane for the package. Soldering the

exposed pad to the PCB increases the reliability of the solder

joints and maximizes the thermal capability of the package.

Typical θ

is specified for a 4-layer PCB with a solid ground

plane. Airflow improves heat dissipation, which reduces θ

. In

addition, metal in direct contact with the package leads from metal

traces, through holes, ground, and power planes reduces θ

Table 7. Thermal Resistance

Package Type

Airflow

Velocity (m/sec)

1, 2, 4

1, 3, 4

Unit

80-Lead TQFP_EP 0 22.48 4.67 °C/W

Per JEDEC JESD51-7, plus JEDEC JESD25-5 2S2P test board.

Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).

Per MIL-STD-883, Method 1012.1.

Per JEDEC STD, a 7 × 7 via array should be used to achieve this value.

ESD CAUTION

Data Sheet AD9650-EP

Rev. 0 | Page 9 of 12

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NOTES

1. DNC = DO NOT CONNECT.

2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE

PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED

PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.

80 79 78 77 76 71 70 69 68 67 66 6575 74 73 72 64 63 62 61

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

PIN 1

IDENTIFIER

DNC

AVDD

VIN+B

VIN–B

AVDD

RBIAS

VCM

SENSE

VREF

AVDD

VIN–A

VIN+A

AVDD

DNC

CLK+

CLK–

SYNC

D0–

D0+

D1–

D1+

D2–

D2+

DRVDD

D3–

D3+

D4–

D4+

D5–

D5+

DNC

PDWN

OEB

CSB

SCLK/DFS

SDIO/DCS

OR+

OR–

D15+

D15–

D14+

D14–

DRVDD

D13+

D13–

DNC

D6–

D6+

DRVDD

D7–

D7+

D8–

D8+

DCO–

D9–

D9+

DRVDD

D10–

D10+

DCO+

D12+

D12–

DNC

D11–

D11+

DNC

AD9650-EP

TOP VIEW

(Not to Scale)

CONNECT EXPOSED PAD TO GROUND

11312-006

Figure 6. Interleaved Parallel LVDS Pin Configuration (Top View)

Table 8. Pin Function Descriptions (Interleaved Parallel LVDS Mode)

Pin No. Mnemonic Type Description

ADC Power Supplies

12, 25, 34, 47 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal).

63, 64, 67, 68,

73, 74, 77, 78

AVDD Supply Analog Power Supply (1.8 V Nominal).

0 AGND,

Exposed Pad

Ground The exposed thermal pad on the bottom of the package provides the analog ground

for the part. This exposed pad must be connected to ground for proper operation.

ADC Analog

65 VIN+A Input Differential Analog Input Pin (+) for Channel A.

66 VIN−A Input Differential Analog Input Pin (−) for Channel A.

76 VIN+B Input Differential Analog Input Pin (+) for Channel B.

75 VIN−B Input Differential Analog Input Pin (−) for Channel B.

69 VREF Input/output Voltage Reference Input/Output.

70 SENSE Input Voltage Reference Mode Select.

72 RBIAS Input/output External Reference Bias Resistor.

71 VCM Output Common-Mode Level Bias Output for Analog Inputs.

3 CLK+ Input ADC Clock Input—True.

4 CLK− Input ADC Clock Input—Complement.

Digital Input

5 SYNC Input Digital Synchronization Pin. Slave mode only.

P1-P3 P4-P6 P7-P9 P10-P12

AD9650USVZR7-105EP

Mfr. #:

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Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 16Bit 105Msps Dual EP

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AD9650USVZR7-105EP

AD9650USVZR7-105EP

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