M48T201Y-70MH1F Datasheet M48T201Y-70MH1F, M48T201V-85MH1F, M48T201V-85MH1E | P19-P21

M48T201Y, M48T201V Clock operation

19/37

3.5 Setting the alarm clock

Registers 7FFF6h-7FFF2h contain the alarm settings. The alarm can be configured to go off

at a prescribed time on a specific month, day of month, hour, minute, or second or repeat

every month, day of month, hour, minute, or second.

It can also be programmed to go off while the M48T201Y/V is in the battery backup to serve

as a system wake-up call.

Bits RPT5-RPT1 put the alarm in the repeat mode of operation. Tabl e 6 shows the possible

configurations. Codes not listed in the table default to the once per second mode to quickly

alert the user of an incorrect alarm setting.

Note: User must transition address (or toggle chip enable) to see flag bit change.

When the clock information matches the alarm clock settings based on the match criteria

defined by RPT5-RPT1, the AF (alarm flag) is set. If AFE (alarm flag enable) is also set, the

alarm condition activates the IRQ

/FT pin. To disable alarm, write ’0’ to the alarm-date

/FT output is cleared by a READ to the flags register as

shown in Figure 7. A subsequent READ of the flags register is necessary to see that the

value of the alarm flag has been reset to '0.'

The IRQ

/FT pin can also be activated in the battery backup mode. The IRQ/FT will go low if

an alarm occurs and both ABE (alarm in battery backup mode enable) and AFE are set. The

ABE and AFE bits are reset during power-up, therefore an alarm generated during power-up

will only set AF. The user can read the flag register at system boot-up to determine if an

alarm was generated while the M48T201Y/V was in the deselect mode during power-up.

Figure 8 on page 20 illustrates the backup mode alarm timing.

Figure 7. Alarm interrupt reset waveforms

Table 6. Alarm repeat modes

RPT5 RPT4 RPT3 RPT2 RPT1 Alarm setting

1 1 1 1 1 Once per second

1 1 1 1 0 Once per minute

1 1 1 0 0 Once per hour

1 1 0 0 0 Once per day

1 0 0 0 0 Once per month

0 0 0 0 0 Once per year

AI02331

A0-A18

ACTIVE FLAG BIT

ADDRESS 7FFF0h

IRQ/FT

15ns Min

HIGH-Z

Clock operation M48T201Y, M48T201V

20/37

Figure 8. Backup mode alarm waveforms

3.6 Watchdog timer

The watchdog timer can be used to detect an out-of-control microprocessor. The user

programs the watchdog timer by setting the desired amount of timeout into the Watchdog

order bits RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1

second, and 11 = 4 seconds. The amount of timeout is then determined to be the

multiplication of the five-bit multiplier value with the resolution. (For example: writing

00001110 in the watchdog register = 3*1 or 3 seconds).

Note: Accuracy of timer is within ± the selected resolution.

If the processor does not reset the timer within the specified period, the M48T201Y/V sets

the WDF (watchdog flag) and generates a watchdog interrupt or a microprocessor reset.

WDF is reset by reading the flag register (address 7FFF0h).

The most significant bit of the watchdog register is the watchdog steering bit (WDS). When

set to a '0', the watchdog will activate the IRQ

/FT pin when timed-out. When WDS is set to a

'1,' the watchdog will output a negative pulse on the RST

pin for t

REC

. The watchdog register

and the AFE, SQWE, ABE, and FT bits will reset to a '0' at the end of a watchdog timeout

when the WDS bit is set to a '1.'

The watchdog timer can be reset by two methods:

1. a transition (high-to-low or low-to-high) can be applied to the watchdog input pin (WDI)

2. the microprocessor can perform a WRITE of the watchdog register.

The timeout period then starts over. The WDI pin should be tied to V

if not used. The

watchdog will be reset on each transition (edge) seen by the WDI pin.

AI03520

IRQ/FT

HIGH-Z

PFD

(max)

PFD

(min)

AFE bit/ABE bit

AF bit in Flags Register

HIGH-Z

tREC

M48T201Y, M48T201V Clock operation

21/37

In order to perform a software reset of the watchdog timer, the original timeout period can be

written into the watchdog register, effectively restarting the countdown cycle.

Should the watchdog timer time out, and the WDS bit is programmed to output an interrupt,

a value of 00h needs to be written to the watchdog register in order to clear the IRQ

/FT pin.

This will also disable the watchdog function until it is again programmed correctly. A READ

of the flags register will reset the watchdog flag (bit D7; register 7FFF0h).

The watchdog function is automatically disabled upon power-down and the watchdog

/FT pin and the

frequency test function is activated, the watchdog or alarm function prevails and the

frequency test function is denied.

Note: The user must transition the address (or toggle chip enable) to see the flag bit change.

3.7 Square wave output

The M48T201Y/V offers the user a programmable square wave function which is output on

the SQW pin. RS3-RS0 bits located in 7FFF0h establish the square wave output frequency.

These frequencies are listed in Tab le 7 . Once the selection of the SQW frequency has been

completed, the SQW pin can be turned on and off under software control with the square

wave enable bit (SQWE) located in register 7FFF6h.

Table 7. Square wave output frequency

Square wave bits Square wave

RS3RS2RS1RS0FrequencyUnits

0000Hi-Z-

0 0 0 1 32.768 kHz

00108.192kHz

00114.096kHz

01002.048kHz

01011.024kHz

0110512Hz

0111256Hz

1000128Hz

100164Hz

101032Hz

101116Hz

11008Hz

11014Hz

11102Hz

11111Hz

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P37

M48T201Y-70MH1F

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M48T201Y-70MH1F

M48T201Y-70MH1F

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