OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

CPC5712U

P1-P3P4-P6P7-P9P10-P11
I
NTEGRATED
C
IRCUITS
D
IVISION
CPC5712
4 www.ixysic.com R02
1.5 Recommended Operating Conditions
1
Input common-mode current per pin must not exceed limit.
2
Resistive and Capacitive loads on the V
REF
output must remain within these limits.
1.6 Electrical Characteristics
Unless otherwise specified, minimum and maximum
values are guaranteed by production testing.
Typical values are characteristic of the device at 25°C
and are the result of engineering evaluations. They are
provided for informational purposes only and are not
part of the manufacturing testing requirements.
Unless otherwise noted, all electrical specifications
are listed for T
A
=25°C and V
CC
= 3V to 5.5V.
Parameter Symbol Min Max Units
V
CC
V
CC
3.0 5.5 V
Input Common Mode Current
1
| I
CM
|
-12A
V
REF
Loading
2
Resistive
R
REF
20 1000 k
Capacitive
C
REF
-220pF
OUT+ and OUT- Loading
Capacitive
C
OUT
C
OUT
300 pF
Current
I
OUT
-500 +500 A
Operating Temperature
T
A
-40 +85 °C
Parameter Conditions Symbol Min Typ Max Units
DC Characteristics
Supply Voltage
V
CC
3-5.5V
Supply Current
V
REF
and all outputs open,
Pins 14 and 15 = Gnd.
I
CC
V
CC
=3V
1.1 1.42 1.9
mA
V
CC
=5.5V
1.5 1.72 2.4
AC Characteristics
Differential Input Resistance
R
IN
10 - - M
Output Offset Voltage
R
DIFF
= 806k,
V
IN
=0V
V
OUT+
-5 - 5 mV
V
OUT-
-5 - 5 mV
Comparator Input Offset Voltage
R
DIFF
= 806k,
From V
IN
through to the
comparators, Measured at
V
OUT+
and V
OUT-
--20- 20mV
Input Offset Current
I
CM
=0AI
IO
-45 - 45 nA
Reference Voltage
V
CC
=3V, V
CC
=5.5V
I
REF
=0A, I
REF
=-80A
V
REF
1.4 1.5 1.6 V
Common-Mode Rejection Ratio
I
CM
< 12A, 0-120 Hz
CMRR 55 - - dB
Differential Gain 0 < f <
20kHz - 4.85 5.00 5.15 -
Polarity Detection Characteristics
Polarity Detection Threshold Voltage
Differential signal applied to
IN+ and IN-
V
IN
±22 ±37 ±54 mV
Digital Output Characteristics
Output Voltage, High
I
OH
=-5mA V
OH
V
CC
-0.6
--V
Output Voltage, Low
I
OL
=5mA V
OL
--0.4V
I
NTEGRATED
C
IRCUITS
D
IVISION
CPC5712
R02 www.ixysic.com 5
2. Functional Description
2.1 Overview
Clare’s CPC5712 is a generalized building block IC for
telephone systems that is connected, through a
resistor network, to the TIP and RING leads. From the
TIP and RING line voltage, the CPC5712 provides a
buffered and amplified differential linear representation
output voltage, a polarity detect signal, and two
programmable level detect signals. From these
detected levels, certain line conditions can be inferred
such as Line-In-Use and battery presence. The
CPC5712 provides TTL/CMOS compatible outputs for
the polarity and programmable level detectors.
The polarity detect and the two programmable level
detects all incorporate hysteresis to provide noise
immunity and eliminate rapid output state changes in
the presence of large voice signals. Hysteresis
settings for the two programmable level detects are
independently programmable; however, the polarity
hysteresis is internally fixed.
The high and low thresholds of the two programmable
level detectors are set with external resistors, the
selection of which is described below.
Positive polarity, POLARITY = HIGH, is indicated for
an OUT+ level greater than the OUT- level while
negative polarity is indicated for an OUT+ level less
than OUT-. For a logic-high polarity detect output with
a normal battery feed of TIP more positive than RING,
the amplifier IN+ will need to be connected to the TIP
lead via the high impedance input resistors. Detection
and hysteresis thresholds for polarity are internal to
the device.
The CPC5712 is connected to the TIP/RING interface
through a high-impedance resistor divider to attenuate
the signal. The resistors in the divider network
become a distributed resistive isolation barrier
between the high-voltage line side and the low voltage
side. The attenuator and the CPC5712 present a high
impedance to TIP and RING, making the circuit almost
undetectable when used as a monitoring device.
2.2 Line Side Interface
IN+, IN-: Analog inputs. The differential signal across
these inputs is amplified and brought out to the pins
OUT+ and OUT-. A nominal reference voltage bias of
1.5V is applied to IN+ and IN- by circuitry internal to
the chip. Because the voltage across TIP and RING
can be very large, TIP and RING cannot be directly
connected to IN+ and IN-. A resistor divider network
defined by R
IN1
, R
IN2
and R
DIFF
attenuates the high
voltage signal across TIP and RING (see ). The
resulting low voltage differential signal across R
DIFF
is
applied to the inputs IN+ and IN-. Resistors R
IN1
, R
IN2
and R
DIFF
are external resistors that must be supplied
by the user.
Any component sizing and value recommendations
given in the circuits described in this document will
need to be reviewed with regard to the regulatory and
safety requirements for each particular application. For
example, the resistors selected for R
IN1
and R
IN2
,
shown in , are recommended to be a pair of 1206
surface mount size resistors in series to provide for
high-voltage isolation.
2.3 Monitor Output
OUT+, OUT-: Analog outputs. The differential signal
across these outputs is the same as the differential
input signal, except there has been a differential gain
of 5 applied to it. A nominal reference voltage bias of
1.5V is applied to OUT+ and OUT- by circuitry internal
to the chip.
2.4 Detector Outputs
DET2, DET1, POLARITY: Digital outputs. These
signals show whether threshold 2 has been crossed,
threshold 1 has been crossed, and the polarity of the
TIP to RING potential.
When configured as shown in , POLARITY will be high
after the TIP to RING potential (TIP more positive than
RING) has increased to a nominal 2V. POLARITY will
switch low after the TIP to RING voltage decreases to
approximately -2V. For example, if the TIP to RING
voltage starts at -48V, POLARITY will be low. As the
TIP to RING voltage increases to +1V, POLARITY will
remain low. As the TIP to RING voltage increases
beyond it’s internally set positive threshold, the
POLARITY output will switch high. POLARITY will
remain high until the TIP to RING voltage decreases
below it’s internally set negative threshold. Because
these polarity thresholds are set internally they are not
user adjustable.
I
NTEGRATED
C
IRCUITS
D
IVISION
CPC5712
6 www.ixysic.com R02
In the case of the detector 2 switching points, DET2
will be low after the |TIP/RING| voltage has decreased
below a threshold set at V
L2
. DET2 will not transition
high until after the |TIP/RING| voltage has increased
above a threshold set at V
H2
. This |TIP/RING| voltage
will be larger than the threshold set at V
L2
. As an
example, the voltage at V
L2
represents a |TIP/RING|
threshold of 20V and V
H2
represents a TIP/RING
threshold of 22V. DET2 will be low if the |TIP/RING|
voltage decreases below 20V, and it will remain low
until the |TIP/RING| voltage increases above 22V.
DET2 will change states for both positive and negative
values of TIP/RING voltage as represented by
|TIP/RING|. This means that DET2 will also be low if
the TIP/RING voltage decreases below -20V and will
remain low until the TIP/RING voltage increases
beyond -22V. The user must rely on POLARITY to
determine whether the TIP/RING threshold changed
due to a positive or negative differential signal since
DET2 does not contain any polarity information.
DET1 behaves similarly to DET2, except that it is
triggered based on the voltage set at V
L1
and V
H1
.
This means that DET1 will be low after the |TIP/RING|
voltage has decreased below the value set by the
voltage at V
L1
and will not change high until after the
|TIP/RING| voltage has increased above the value set
by the voltage at V
H1
. DET1 does not give any polarity
information for the same reasons as defined for DET2.
In the application circuit provided, the TIP/RING
threshold levels of DET2 will always be higher than the
threshold levels of DET1.
2.5 Detector Threshold Operation
V
L1
, V
H1
, V
L2
, and V
H2
: Inputs used to set the
|TIP/RING| threshold levels that are to be detected.
V
H1
and V
L1
are used to set the high and low threshold
levels. The difference between V
H1
and V
L1
sets the
hysteresis for the 1
st
threshold level. V
H2
and V
L2
are
used to set the threshold and hysteresis for the 2
nd
threshold level. There is a digital output for both the 1
st
and 2
nd
threshold levels that shows when the
|TIP/RING| voltage has crossed a threshold level and
when it has exceeded the configured hysteresis level.
This was explained in the DET1 and DET2 definitions.
In general, the digital output will be low when the
|TIP/RING| voltage has fallen below the V
L#
level and
will change high again once the |TIP/RING| voltage
has risen above the V
H#
level.
V
REF
: An analog output that is similar to the DC bias
level that is applied to OUT+ and OUT-. This voltage is
brought off chip so that it can be used to define
threshold detection levels. Load capacitance on this
pin must be kept less than the value recommended in
the table Recommended Operating Conditions.
The total load resistance on this pin must be within the
range specified in the table Recommended
Operating Conditions.
Resistors R1, R2, R3, R4 and R5 are external
resistors, which must be provided by the user. The
selection of the resistors determines the voltages at
V
L2
, V
H2
, V
L1
and V
H1
and therefore the threshold and
hysteresis values for the 2 detectors.
The values for R1, R2, R3, R4, and R5 are easily
determined. Select voltage levels for the 1
st
and 2
nd
threshold and hysteresis settings such that:
V
H2
> V
L2
> V
H1
> V
L1
Then use the following algorithm to find the values of
R2, R3, R4 and R5.
1. Select a value for R1.
2. R2 = (R1(V
H1
-V
L1
)) / V
L1
3. R3 = (R1(V
L2
-V
H1
))/ V
L1
4. R4 = (R1(V
H2
-V
L2
)) / V
L1
5. R5 = (R1(V
REF
/A-V
H2
)) / V
L1
• V
REF
= 1.5V
• A = (2.5 (R
DIFF
)) / (R
IN1
+ R
IN2
+ R
DIFF
), which
typically calculates to 0.05; in this case: 0.04938.
See Figure 1.
Also, as shown in the table of Recommended
Operating Conditions, the resistive load on the V
REF
pin must fall within the range:
20k < (R1 + R2 + R3 + R4 + R5) < 1M
2.6 Power Connections
VCC, Ground: Power supply pins. These are used to
supply voltage and ground to the chip.
P1-P3P4-P6P7-P9P10-P11

CPC5712U

Mfr. #:
Buy CPC5712U
Manufacturer:
IXYS Integrated Circuits
Description:
Supervisory Circuits Phone Line Monitor
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet