CAT24C164
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7
SLAVE
ADDRESS
S
A
C
K
A
C
K
S
T
O
P
P
S
T
A
R
T
A
C
K
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
DATA
BYTE
Figure 6. Byte Write Sequence
a
7
a
0
d
7
d
0
Figure 7. Write Cycle Timing
STOP
CONDITION
START
CONDITION
ADDRESS
ACK8th Bit
Byte n
SCL
SDA
t
WR
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
S
T
A
R
T
A
C
K
S
T
O
P
P
A
C
K
BUS
ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+P
Figure 8. Page Write Sequence
n = 1
P 15
Figure 9. WP Timing
189
1
8
ADDRESS
BYTE
DATA
BYTE
SCL
SDA
WP
t
SU:WP
t
HD:WP
a
7
a
0
d
7
d
0
CAT24C164
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8
READ OPERATIONS
Immediate Read
Upon receiving a Slave address with the R/W bit set to ‘1’,
the CAT24C164 will interpret this as a request for data
residing at the current byte address in memory. The
CAT24C164 will acknowledge the Slave address, will
immediately shift out the data residing at the current address,
and will then wait for the Master to respond. If the Master
does not acknowledge the data (NoACK) and then follows
up with a STOP condition (Figure 10), the CAT24C164
returns to Standby mode.
Selective Read
Selective Read operations allow the Master device to
select at random any memory location for a read operation.
The Master device first performs a ‘dummy’ write operation
by sending the START condition, slave address and byte
address of the location it wishes to read. After the
CAT24C164 acknowledges the byte address, the Master
device resends the START condition and the slave address,
this time with the R/W
bit set to one. The CAT24C164 then
responds with its acknowledge and sends the requested data
byte. The Master device does not acknowledge the data
(NoACK) but will generate a STOP condition (Figure 11).
Sequential Read
If during a Read session, the Master acknowledges the 1
st
data byte, then the CAT24C164 will continue transmitting
data residing at subsequent locations until the Master
responds with a NoACK, followed by a STOP (Figure 12).
In contrast to Page Write, during Sequential Read the
address count will automatically increment to and then
wraparound at end of memory (rather than end of page).
Figure 10. Immediate Read Sequence and Timing
SCL
SDA 8th Bit
STOP
NO ACKDATA OUT
89
SLAVE
ADDRESS
S
A
C
K
DATA
BYTE
N
O
A
C
K
S
T
O
P
P
S
T
A
R
T
BUS ACTIVITY:
MASTER
SLAVE
Figure 11. Selective Read Sequence
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
S
T
A
R
T
S
S
T
A
R
T
P
S
T
O
P
ADDRESS
BYTE
N
O
A
C
K
DATA
BYTE
BUS ACTIVITY:
MASTER
SLAVE
SLAVE
ADDRESS
Figure 12. Sequential Read Sequence
S
T
O
P
P
SLAVE
ADDRESS
A
C
K
A
C
K
A
C
K
N
O
A
C
K
A
C
K
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+2
DATA
BYTE
n+x
BUS ACTIVITY:
MASTER
SLAVE
CAT24C164
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9
PACKAGE DIMENSIONS
PDIP8, 300 mils
CASE 646AA01
ISSUE A
E1
D
A
L
eb
b2
A1
A2
E
eB
c
TOP VIEW
SIDE VIEW END VIEW
PIN # 1
IDENTIFICATION
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
SYMBOL
MIN NOM MAX
A
A1
A2
b
b2
c
D
e
E1
L
0.38
2.92
0.36
6.10
1.14
0.20
9.02
2.54 BSC
3.30
5.33
4.95
0.56
7.11
1.78
0.36
10.16
eB
7.87 10.92
E 7.62 8.25
2.92 3.80
3.30
0.46
6.35
1.52
0.25
9.27
7.87

CAT24C164LI-G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
EEPROM 16K-Bit Serial Cascadable
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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