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SI5330A-A00202-GM

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
Rev. 1.0 4/12 Copyright © 2012 by Silicon Laboratories Si5330
Si5330
1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW
C
LOCK BUFFER/LEVEL TRANSLATOR
Features
Applications
Functional Block Diagram
Supports single-ended or
differential input clock signals
Generates four differential
(LVPECL, LVDS, HCSL) or eight
single-ended (CMOS, SSTL,
HSTL) outputs
Provides signal level translation
Differential to single-ended
Single-ended to differential
Differential to differential
Single-ended to single-ended
Wide frequency range
LVPECL, LVDS: 5 to 710 MHz
HCSL: 5 to 250 MHz
SSTL, HSTL: 5 to 350 MHz
CMOS: 5 to 200 MHz
Additive jitter: 150 fs RMS typ
Output-output skew: 100 ps
Propagation delay: 2.5 ns typ
Single core supply with excellent
PSRR: 1.8, 2.5, or 3.3 V
Output driver supply voltage
independent of core supply: 1.5,
1.8, 2.5, or 3.3 V
Loss of Signal (LOS) indicator
allows system clock monitoring
Output Enable (OEB) pin allows
glitchless control of output clocks
Low power: 10 mA typical core
current
Industrial temperature range:
–40 to +85
°
C
Small size: 24-lead, 4 x 4 mm
QFN
High Speed Clock Distribution
Ethernet Switch/Router
SONET / SDH
PCI Express 2.0/3.0
Fibre Channel
MSAN/DSLAM/PON
Telecom Line Cards
Single-ended
or
Differential
Single-ended
or
Differential
Si5330
OEB
Control
LOS
IN
V
DD
V
DDO0
CLK0
V
DDO1
CLK1
V
DDO2
CLK2
V
DDO3
CLK3
Ordering Information:
See page 14.
Pin Assignments
IN3
IN2
RSVD_GND
IN1
CLK2B
CLK2A
VDDO2
VDDO1
CLK1B
CLK1A
VDD
RSVD_GND
VDD
RSVD_GND
CLK3A
CLK3B
LOS
OEB
VDDO0
CLK0B
CLK0A
VDDO3
GND
GND
RSVD_GND
RSVD_GND
24
23 22 21 20 19
7
8 9 10 11 12
54
321
6
14 15
16 17 18
13
Si5330
2 Rev. 1.0
1. Functional Block Diagrams Based on Orderable Part Number
*
Figure 1. Si5330 Functional Block Diagrams
*Note: See Table 11 for detailed ordering information.
OEB
Control
LOS
IN1
V
DDO1
V
DDO2
V
DDO3
V
DDO0
Si5330A/B/C
IN2
CLK0A
CLK0B
CLK1A
CLK1B
CLK2A
CLK2B
CLK3A
CLK3B
1:4 Differential to Differential Buffer
IN3
1:8 Single-Ended to Single-Ended Buffer
OEB
Control
CLK0A
LOS
IN3
V
DDO1
V
DDO2
V
DDO3
V
DDO0
Si5330F
CLK0B
CLK1A
CLK1B
CLK2A
CLK2B
CLK3A
CLK3B
IN1
IN2
1:8 Differential to Single-Ended Buffer
OEB
Control
CLK0A
LOS
IN1
V
DDO1
V
DDO2
V
DDO3
V
DDO0
Si5330G/H/J
CLK0B
CLK1A
CLK1B
CLK2A
CLK2B
CLK3A
CLK3B
IN2
IN3
OEB
Control
LOS
IN3
V
DDO1
V
DDO2
V
DDO3
V
DDO0
Si5330K/L/M
CLK0A
CLK0B
CLK1A
CLK1B
CLK2A
CLK2B
CLK3A
CLK3B
1:4 Single-Ended to Differential Buffer
IN1
IN2
Si5330
Rev. 1.0 3
TABLE OF CONTENTS
Section Page
1. Functional Block Diagrams Based on Orderable Part Number* . . . . . . . . . . . . . . . . . . .2
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.1. VDD and VDDO Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.2. Loss Of Signal Indicator (LOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.3. Output Enable (OEB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.4. Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.5. Output Driver Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.6. Input and Output Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4. Ordering the Si5330 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
6. Orderable Part Numbers and Device Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
7. Package Outline: 24-Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
8. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
9. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
9.1. Si5330 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
9.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

SI5330A-A00202-GM

Mfr. #:
Buy SI5330A-A00202-GM
Manufacturer:
Silicon Labs
Description:
Clock Buffer Differential input, 2.5V LVPECL output, 1:4 clock buffer, 5 - 710 MHz
Lifecycle:
New from this manufacturer.
Delivery:
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