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IXFQ24N50P2

P1-P3P4-P5
IXYS Reserves the Right to Change Limits, Test Conditions, and Dimensions.
IXFQ24N50P2
Fig. 7. Input Admittance
0
5
10
15
20
25
30
35
3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
V
GS
- Volts
I
D
- Amperes
T
J
= 125ºC
25ºC
- 40ºC
Fig. 8. Transconductance
0
10
20
30
40
50
0 5 10 15 20 25 30 35
I
D
- Amperes
g
f s
- Siemens
T
J
= - 40ºC
125ºC
25ºC
Fig. 9. Forward Voltage Drop of Intrinsic Diode
0
10
20
30
40
50
60
70
80
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
V
SD
- Volts
I
S
- Amperes
T
J
= 125ºC
T
J
= 25ºC
Fig. 10. Gate Charge
0
2
4
6
8
10
0 5 10 15 20 25 30 35 40 45 50
Q
G
- NanoCoulombs
V
GS
- Volts
V
DS
= 250V
I
D
= 12A
I
G
= 10mA
Fig. 11. Capacitance
10
100
1,000
10,000
0 5 10 15 20 25 30 35 40
V
DS
- Volts
Capacitance - PicoFarads
f
= 1 MHz
C
iss
C
rss
C
oss
Fig. 12. Forward-Bias Safe Operating Area
0.01
0.1
1
10
100
10 100 1000
V
DS
- Volts
I
D
- Amperes
T
J
= 150ºC
T
C
= 25ºC
Single Pulse
25µs
1ms
100µs
R
DS(on)
Limit
10ms
© 2011 IXYS CORPORATION, All Rights Reserved
IXYS REF: F_24N50P2(57-N45)6-03-10-A
IXFQ24N50P2
Fig. 13. Maximum Transient Thermal Impedance
0.001
0.01
0.1
1
0.00001 0.0001 0.001 0.01 0.1 1
Pulse Width - Second
Z
(th)JC
- ºC / W
P1-P3P4-P5

IXFQ24N50P2

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Buy IXFQ24N50P2
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Description:
500V POLAR2 HIPERFETS
Lifecycle:
New from this manufacturer.
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