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MAX1875AEEG+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
MAX1858A/MAX1875A/MAX1876A
Dual 180° Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
16 ______________________________________________________________________________________
inductor’s saturation rating must exceed the peak-
inductor current at the maximum defined load current
(I
LOAD(MAX)
):
Setting the Valley Current Limit
The minimum current-limit threshold must be high
enough to support the maximum expected load current
with the worst-case low-side MOSFET on-resistance
value since the low-side MOSFET’s on-resistance is
used as the current-sense element. The inductor’s valley
current occurs at I
LOAD(MAX)
minus half of the ripple
current. The current-sense threshold voltage (V
ITH
)
should be greater than voltage on the low-side MOSFET
during the ripple-current valley:
where R
DS(ON)
is the on-resistance of the low-side
MOSFET (N
L
). Use the maximum value for R
DS(ON)
from the low-side MOSFET’s data sheet, and additional
margin to account for R
DS(ON)
rise with temperature is
also recommended. A good general rule is to allow
0.5% additional resistance for each °C of the MOSFET
junction temperature rise.
Connect ILIM_ to VL for the default 100mV (typ) cur-
rent-limit threshold. For an adjustable threshold, con-
nect a resistor (R
ILIM
_) from ILIM_ to GND. The
relationship between the current-limit threshold (V
ITH
_)
and R
ILIM
_ is:
where R
ILIM
_ is in Ω and V
ITH
_ is in V.
An R
ILIM
resistance range of 100kΩ to 600kΩ corre-
sponds to a current-limit threshold of 50mV to 300mV.
When adjusting the current limit, 1% tolerance resistors
minimize error in the current-limit threshold.
For foldback current limit, a resistor (R
FBI
) is added
from ILIM pin to output. The value of R
ILIM
and R
FBI
can then be calculated as follows:
First select the percentage of foldback, P
FB
, from 15%
to 30%, then:
If R
ILIM_
results in a negative number, select a low-side
MOSFET with lower R
DS(ON)
or increase P
FB_
or a com-
bination of both for the best compromise of cost, effi-
ciency, and lower power dissipation during short circuit.
Input Capacitor
The input filter capacitor reduces peak currents drawn
from the power source and reduces noise and voltage
ripple on the input caused by the circuit’s switching.
The input capacitor must meet the ripple current
requirement (I
RMS
) imposed by the switching currents
as defined by the following equation:
I
RMS
has a maximum value when the input voltage equals
twice the output voltage (V
IN
= 2V
OUT
), so I
RMS(MAX)
=
I
LOAD
/ 2. For most applications, nontantalum capacitors
(ceramic, aluminum, polymer, or OS-CON) are preferred
at the input due to their robustness with high inrush cur-
rents typical of systems that can be powered from very
low impedance sources. Additionally, two (or more)
smaller-value low-ESR capacitors can be connected in
parallel for lower cost. Choose an input capacitor that
exhibits less than +10°C temperature rise at the RMS
input current for optimal long-term reliability.
Output Capacitor
The key selection parameters for the output capacitor
are capacitance value, ESR, and voltage rating. These
parameters affect the overall stability, output ripple volt-
age, and transient response. The output ripple has two
components: variations in the charge stored in the out-
put capacitor, and the voltage drop across the capaci-
tor’s ESR caused by the current flowing into and out of
the capacitor:
VV V
RIPPLE RIPPLE ESR RIPPLE C
≅ +
() ()
II
VVV
V
RMS LOAD
OUT IN OUT
IN
=
()-
R
PV
P
and
R
VPR
VVP
FBI
FB OUT
FB
ILIM
ITH FB FBI
OUT ITH FB
=
×
×
=
××
×
[]
510 1
10 1
10 1
6-
-
-
--
()
()
()
R
V
A
ILIM
ITH
_
_
.
=
µ05
VR I
LIR
ITH DS ONMAX LOAD MAX
>××
⎛
⎝
⎜
⎞
⎠
⎟
(, ) ( )
1
2
-
II
LIR
I
PEAK LOAD MAX LOAD MAX
=+
⎛
⎝
⎜
⎞
⎠
⎟
() ()
2
MAX1858A/MAX1875A/MAX1876A
Dual 180° Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
______________________________________________________________________________________ 17
The output voltage ripple as a consequence of the ESR
and output capacitance is:
where I
P-P
is the peak-to-peak inductor current (see the
Inductor Selection section). These equations are suitable
for initial capacitor selection, but final values should be
verified by testing in a prototype or evaluation circuit.
As a general rule, a smaller inductor ripple current results
in less output ripple voltage. Since inductor ripple current
depends on the inductor value and input voltage, the out-
put ripple voltage decreases with larger inductance and
increases with higher input voltages. However, the induc-
tor ripple current also impacts transient-response perfor-
mance, especially at low V
IN
- V
OUT
differentials. Low
inductor values allow the inductor current to slew faster,
replenishing charge removed from the output filter capac-
itors by a sudden load step. The amount of output-volt-
age sag is also a function of the maximum duty factor,
which can be calculated from the minimum off-time and
switching frequency:
where t
OFF(MIN)
is the minimum off-time (see the
Electrical Characteristics), and f
SW
is set by R
OSC
(see
the Setting the Switching Frequency section).
Compensation
Each voltage-mode controller section employs a
transconductance error amplifier whose output is the
compensation point of the control loop. The control loop
is shown in Figure 9. For frequencies much lower than
Nyquist, the PWM block can be simplified to a voltage
amplifier. Connect R
COMP_
and C
COMP_A
from COMP
to GND to compensate the loop (Figure 9). The inductor,
output capacitor, compensation resistor, and compen-
sation capacitors determine the loop stability. Since the
inductor and output capacitor are chosen based on per-
formance, size, and cost, select the compensation resis-
tor and capacitors to optimize control-loop stability.
To determine the loop gain (A
L
), consider the gain from
FB to COMP (A
COMP/FB
), from COMP to LX (A
LX/COMP
),
and from LX to FB (A
FB/LX
). The total loop gain is:
where:
assuming an ideal integrator, and assuming that
C
COMP_B
is much less than C
COMP_A
:
where V
RAMP
= 1V
P-P
:
Therefore:
For an ideal integrator, this loop gain approaches infinity
at DC. In reality the g
M
amplifier has a finite output
impedance, which imposes a finite, but large, loop gain.
It is this large loop gain that provides DC load accuracy.
The dominant pole occurs due to the integrator, and for
this analysis, it can be approximated to occur at DC.
R
COMP
creates a zero at:
The inductor and capacitor form a double pole at:
f
LC
LC
OUT
=
×
1
2π
f
RC
Z COMP A
COMP COMP A
__
__
=
×
1
2π
A
g
SC
SR C
SR C
V
V
V
V
SR C
SLC
L
M COMP
COMP A
COMP COMP A
COMP COMP B
IN
RAMP
SET
OUT
ESR OUT
OUT
≅ ×
+
+
×
××
+
+
_
_
_
_
1
1
1
1
2
A
V
V
V
V
sR C
SLC SR C
V
V
SR C
VSLC
FB LX
FB
LX
SET
OUT
ESR OUT
OUT ESR OUT
SET
OUT
ESR OUT
OUT OUT
/
==
+
++
≅
+
+
1
1
1
1
2
2
A
V
V
V
V
LX COMP
LX
COMP
IN
RAMP
/
==
A
V
V
g
SC
sR C
sR C
COMP FB
COMP
FB
M COMP
COMP
COMP COMP A
COMP COMP B
/
_
_
_
= ≅ ×
+
+
1
1
AAAA
L COMP FB LX COMP FB LX
=××
// /
V
LI I
V
Vf
t
CV
VV
Vf
t
SAG
LOAD LOAD
OUT
IN SW
OFF MIN
OUT OUT
IN OUT
IN SW
OFF MIN
=
⎛
⎝
⎜
⎞
⎠
⎟
+
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
⎛
⎝
⎜
⎞
⎠
⎟
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
()
()
()
12
2
2
-
-
-
VIR
V
I
Cf
I
VV
fL
V
V
RIPPLE ESR P P ESR
RIPPLE C
PP
OUT SW
PP
IN OUT
SW
OUT
IN
()
()
=
=
=
⎛
⎝
⎜
⎞
⎠
⎟
⎛
⎝
⎜
⎞
⎠
⎟
-
-
-
-
8
MAX1858A/MAX1875A/MAX1876A
Dual 180° Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
18 ______________________________________________________________________________________
At some higher frequency, the output capacitor’s
impedance becomes insignificant compared to its ESR,
and the LC system becomes more like an LR system,
turning a double pole into a single pole. This zero
occurs at:
A final pole is added using C
COMP_B
to reduce the
gain and attenuate noise after crossover. This pole
(f
COMP_B
) occurs at:
Figure 10 shows a Bode plot of the poles and zeros in
their relative locations.
Near crossover, the following approximations can be
made to simplify the loop-gain equation:
•R
COMP
has much higher impedance than C
COMP
.
This is true if, and only if, crossover occurs above
f
Z_COMP_A
. If this is true, C
COMP_A
can be ignored
(as a short to ground).
•R
ESR
is much higher impedance than C
OUT
. This is
true if, and only if, crossover occurs well after the out-
put capacitor’s ESR zero. If this is true, C
OUT
becomes an insignificant part of the loop gain and can
be ignored (as a short to ground).
•C
COMP_B
is much higher impedance than R
COMP
and can be ignored (as an open circuit). This is true
if, and only if, crossover occurs far below f
COMP_B
.
The following loop-gain equation can be found by using
these previous approximations with Figure 9:
Setting the loop gain to 1 and solving for the crossover
frequency yields:
To ensure stability, select R
COMP
to meet the following
criteria:
• Unity-gain crossover must occur below 1/5th of the
switching frequency.
• For reasonable phase margin using type 1 compen-
sation, f
CO
must be larger than 5
✕
f
ESR
.
Choose C
COMP_A
so that f
Z_COMP_A
equals half f
LC
using the following equation:
Choose C
COMP_B
so that f
COMP_B
occurs at 3 times
f
CO
using the following equation:
C
fR
COMP B
CO COMP
_
=
××
()
×
1
23π
C
LC
R
COMP A
OUT
COMP
_
=
×2
f GBW
V
V
V
V
gRR
L
CO
IN
RAMP
SET
OUT
M COMP COMP ESR
== ×
×
××
×
_
2π
A
V
V
V
V
gRR
sL
L
IN
RAMP
SET
OUT
M COMP COMP ESR
≅ ××
××
_
f
RC
COMP B
COMP COMP B
_
_
=
×
1
2π
f
RC
ESR
ESR OUT
=
×
1
2π
COMP_
R
COMP_
C
COMP_A
C
COMP_B
g
M_COMP
P
W
M
V
C
V
SET
DH
DL
N
N
L
LX
FB
V
OUT
R
ESR
C
OUT
COMP_
R
COMP_
C
COMP_A
C
COMP_B
g
M_COMP
V
SET
L
LX
FB
R
ESR
C
OUT
GAIN = +V
IN
/V
RAMP
=
Figure 9. Fixed-Frequency Voltage-Mode Control Loop
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

MAX1875AEEG+

Mfr. #:
Buy MAX1875AEEG+
Manufacturer:
Maxim Integrated
Description:
Switching Controllers Dual 180 Out PWM Step-Down
Lifecycle:
New from this manufacturer.
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